Datasheet
TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
MAIN MANUAL
Various Configuration Registers: S/D, Synchronization, etc.
Various Configuration Registers: Closed-loop, Switches…
R/W
Addr
Bit
Val
Description
RW
0x10
15:0
STP_LENGTH_ADD (Default: 0x0000)
U
Additional length [# clock cycles] for active step polarity of a step at STPOUT.
31:16
DIR_SETUP_TIME (Default: 0x0000)
U
Delay [# clock cycles] between DIROUT and STPOUT voltage level changes.
0x11
31:0
START_OUT_ADD (Default:0x00000000)
U
Additional length [# clock cycles] for active start signal.
Active start signal length = 1+START_OUT_ADD
0x12
31:0
GEAR_RATIO (Default:0x01000000)
S
Constant value that is added to the internal position counter by an active step at
STPIN. Value representation: 8 digits and 24 decimal places.
0x13
31:0
START_DELAY (Default:0x00000000)
U
Delay time [# clock cycles] between start trigger and internal start signal release.
0x14
31:0
CLK_GATING_DELAY
(Default:0x00000000)
U
Delay time [# clock cycles] between clock gating trigger and clock gating start.
0x1D
23:0
SPI_SWITCH_VEL
U
Absolute velocity value [pps] at which automatic cover datagrams are sent
31:0
2
nd
assignment: Also used as
DAC_ADDR_A/B if SPI-DAC mode is enabled
(see 19.30. )
0x1E
15:0
HOME_SAFETY_MARGIN (Default: 0x0000)
U
HOME_REF polarity can be invalid within
X_HOME
±
HOME_SAFETY_MARGIN,
which is not flagged as error.
0x1F
11:0
CHOPSYNC_DIV (Default: 0x0280)
(ChopSync for TMC23x/24x is enabled)
U
Chopper clock divider that defines the chopper frequency f
OSC
:
f
OSC
= f
CLK
/
CHOPSYNC_DIV
with 96 ≤
CHOPSYNC_DIV
≤ 818
15:0
2
nd
assignment: Also used as
PWM_FREQ
if Voltage PWM is enabled (see 19.17. )
W
0x60
31:0
FS_VEL(Default:0x000000)
(Closed-loop and dcStep operation are disabled)
U
Minimum fullstep velocity [pps].
In case |
VACTUAL
| >
FS_VEL
fullstep operation is active, if enabled.
2
nd
assignment: Also used as
DC_VEL
if dcStep is enabled (see section 19.27. )
3
rd
assignment: Also used as
CL_VMIN_EMF
if closed-loop is enabled (see 19.26. )
0x64
31:0
Reserved. Set to 0x00000000.
0x67
23:0
VSTALL_LIMIT (Default:0x00000000)
U
Stop on stall velocity limit [pps]:
Only above this limit an active stall leads to a stop on stall, if enabled.
0x7B
31:0
TZEROWAIT (Default:0x00000000)
U
Standstill phase after reaching
VACTUAL
= 0.
R
2
nd
assignment: Also used as
CURRENTA/B_SPI
for read out (see section 19.29. )
W
0x7C
31:0
CIRCULAR_DEC (Default:0x00000000)
U
Decimal places for circular motion if one revolution is not exactly mapped to an
even number of µSteps per revolution. Value representation: 1 digit, 31 decimals.
R
8:0
2
nd
assignment: Also used as
SCALE_PARAM
for read out (see section 19.8. )
Table 80: Various Configuration Registers: S/D, Synchronization, etc.