Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Event Selection Registers 0x0B..0X0D
Event Selection Registers
R/W
Addr
Bit
Remarks
RW
0x0B
SPI_STATUS_SELECTION (Default: 0x82029805)
31:0
Events selection for SPI datagrams:
Event bits of EVENTS register 0x0E that are selected (=1) in this register are
forwarded to the eight status bits that are transferred with every SPI datagram (first
eight bits from LSB are significant!).
0x0C
EVENT_CLEAR_CONF ( Default: 0x00000000)
31:0
Event protection configuration:
Event bits of EVENTS register 0x0E that are selected in this register (=1) are not
cleared during the readout process of EVENTS register 0x0E.
0x0D
INTR_CONF ( Default: 0x00000000)
31:0
Event selection for INTR output:
All Event bits of EVENTS register 0x0E that are selected here (=1) are ORed with
interrupt event register set:
if any of the selected events is active, an interrupt at INTR is generated.
Table 77: Event Selection Regsiters 0x0B…0x0D