Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
SPI Timing Description
The SPI interface is synchronized to the internal system clock, which limits SPI bus clock SCKIN
to a quarter of the system clock frequency. The signal processing of SPI inputs is supported
with internal Schmitt Trigger, but not with RC elements.
NOTE:
 In order to avoid glitches at the inputs of the SPI interface between µC and TMC4361A, external RC
elements have to be provided.
Figure 14 shows the timing parameters of an SPI bus transaction, and the table below specifies the parameter
values.
SPI Interface Timing
SPI Interface Timing
AC Characteristics: External clock period: t
CLK
Parameter
Symbol
Conditions
Min
Type
Max
Unit
SCKIN valid before or after
change of NSCSIN
t
CC
10
ns
NSCSIN high time
t
CSH
Min. time is for
synchronous CLK with
SCKIN high one t
CH
before SCSIN high only.
t
CLK
>2·t
CLK
+10
ns
SCKIN low time
t
CL
Min. time is for
synchronous CLK only.
t
CLK
>t
CLK
+10
ns
SCKIN high time
t
CH
Min. time is for
synchronous CLK only.
t
CLK
>t
CLK
+10
ns
SCKIN frequency using
external clock
(Example: f
CLK
= 16 MHz)
f
SCK
Assumes synchronous
CLK.
f
CLK
/ 4
(4)
MHz
SDIIN setup time before
rising edge of SCKIN
t
DU
10
ns
SDIIN hold time after rising
edge of SCKIN
t
DH
10
ns
Data out valid time after
falling SCKIN clock edge
t
DO
No capacitive load on
SDOIN.
t
FILT
+5
ns
Table 5: SPI Interface Timing
i t
CLK
= 1 / f
CLK