Datasheet
TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
183/230
© 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights
to technical change reserved. Download newest version at: www.trinamic.com .
Read entire documentation; especially the “Supplemental Directives” on page 224.
MAIN MANUAL
Input Filter Configuration Register INPUT_FILT_CONF 0x03
INPUT_FILT_CONF 0x03
(Default value: 0x00000000)
R/W
Bit
Val
Remarks
RW
2:0
SR_ENC_IN
U
Input sample rate = f
clk
/ 2
SR_ENC_IN
for the following pins:
A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG
3
Reserved. Set to 0.
6:4
FILT_L_ENC_IN
U
Filter length for these pins: A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG.
Number of sample input bits that must have equal voltage levels to provide a valid
input bit.
7
SD_FILT0
0
S/D input pins (STPIN/DIRIN) are not assigned to the ENC_IN input filter group.
1
S/D input pins (STPIN/DIRIN) are also assigned to the ENC_IN input filter group.
10:8
SR_REF
U
Input sample rate = f
clk
/ 2
REF
for the following pins: STOPL, HOME_REF, STOPL
11
Reserved. Set to 0.
14:12
FILT_L_REF
U
Filter length for the following pins: STOPL, HOME_REF, STOPL. Number of sample
input bits that must have equal voltage levels to provide a valid input bit.
15
SD_FILT1
0
S/D input pins (STPIN/DIRIN) are not assigned to the REF input filter group.
1
S/D input pins (STPIN/DIRIN) are also assigned to the REF input filter group.
18:16
SR_S
U
Input sample rate = f
clk
/ 2
S
for the START pin.
19
Reserved. Set to 0.
22:20
FILT_L_S
U
Filter length for the START pin. Number of sample input bits that must have equal
voltage levels to provide a valid input bit.
23
SD_FILT2
0
S/D input pins (STPIN/DIRIN) are not assigned to the S input filter group.
1
S/D input pins (STPIN/DIRIN) are also assigned to the S input filter group.
26:24
SR_ENC_OUT
U
Input sample rate = f
clk
/ 2
SR_ENC_OUT
for these pins: SDODRV_SCLK, SDIDRV_NSCLK
27
Reserved. Set to 0.
30:28
FILT_L_ENC_OUT
U
Filter length for the following pins: SDODRV_SCLK, SDIDRV_NSCLK. Number of
sample input bits that must have equal voltage levels to provide a valid input bit.
31
SD_FILT3
0
S/D input pins (STPIN/DIRIN) are not assigned to the ENC_OUT input filter group.
1
S/D input pins (STPIN/DIRIN) are assigned to the ENC_OUT input filter group.
Table 68: Input Filter Configuration Register INPUT_FILT_CONF 0x03