Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
All data is right-aligned. Some registers represent unsigned (positive) values; others
represent integer values (signed) as two’s complement numbers.
Some registers consist of switches that are represented as bits or bit vectors.
The SPI transaction process is as follows:
 The slave is enabled for SPI transaction by a transition to low level on the chip
select input NSCSIN.
 Bit transfer is synchronous to the bus clock SCKIN, with the slave latching the
data from SDIIN on the rising edge of SCKIN and driving data to SDOIN
following the falling edge.
 The most significant bit is sent first.
i A minimum of 40 SCKIN clock cycles is required for a bus transaction with
TMC4361A.
Take the following aspects into consideration:
 Whenever data is read from or written to the TMC4361A, the first eight
bits that are delivered back contain the SPI status SPI_STATUS that consists of
eight user-selected event bits. The selection of these bits are explained in
chapter 5.2. (Page 26).
 If less than 40 clock cycles are transmitted, the transfer is not valid; even
for read access. However, sending only eight clock cycles can be useful to
obtain the SPI status because it sends the status information back first.
 If more than 40 clocks cycles are transmitted, the additional bits shifted
into SDIIN are shifted out on SDOIN after a 40-clock delay through an internal
shift register. This can be used for daisy chaining multiple chips.
 NSCSIN must be low during the whole bus transaction. When NSCSIN
goes high, the contents of the internal shift register are latched into the internal
control register and recognized as a command from the master to the slave. If
more than 40 bits are sent, only the last 40 bits received - before the rising
edge of NSCSIN - are recognized as the command.
Figure 14: SPI Timing Datagram
NSCSIN
SCKIN
SDIIN
SDOIN
t
CC
t
CC
t
CL
t
CH
bit39 bit38 bit0
bit39 bit38 bit0
t
DO
t
ZC
t
DU
t
DH
t
CH
Data Alignment
SPI Transaction
Process
AREAS OF
SPECIAL
CONCERN
System
Behavior
Specifics
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