Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
It is possible to use TMC4361A standby phase to automatically activate clock gating.
i For further information about standby timer, see section 11.1. , page 121.
In order to activate automatic clock gating, do as follows:
Action:
 Set the time frame for STDBY_DEALY register 0x15 after ramp stop, and before
standby phase starts.
 Set hold_current_scale_en = 1 ( CURRENT_CONF register 0x05).
 Set closed_loop_scale_en = 0 ( CURRENT_CONF register 0x05).
 Set clk_gating_en = 1 (bit17 of GENERAL_CONF register 0x00).
 Set proper CLK_GATING_DELAY register 0x14.
 Set clk_gating_stdby_en = 1 (bit17 of GENERAL_CONF register 0x00).
Result:
After standby phase activation, activation of clock gating counter follows. When the
counter reaches 0, clock gating is activated.
In addition, the start signal generation, presented in chapter 9, page 69, can be used
for an automated wake-up. An example is given in the figure below.
The chart below shows the TARGET_REACHED (=TR) signal, which signifies ramp stop
at which VACTUAL reaches 0.
When VACTUAL = 0, the following process occurs:
1. The start delay timer signifies the time frame between ramp stop and next ramp
start.
2. When the standby delay timer expires, the standby phase is activated.
3. When the standby phase is activated, the clock gating delay timer is started.
4. After the clock gating delay timer expires, clock gating is activated.
5. Shortly before the start delay timer expires, clock gating is disabled, which occurs
so that the next ramp is started with proper assigned registers.
Figure 71: Automatic Clock Gating Activation and Wake-Up
Internal clk
signal
START_DELAY
External
clk signal
STDBY_DELAY
CLK_GATING_DELAY
Clock gating
delay timer
Stdby delay
timer
START
delay timer
TR
Automatic Clock
Gating
Procedure