Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
Clock gating must be enabled before activation. In addition, the delay between
activation and the active clock gating phase can be configured.
In order to activate clock gating manually, do as follows:
PRECONDITION: VEL_STATE_F = “00” INDICATING THAT VACTUAL = 0.
Action:
 Set clk_gating_en = 1 (bit17 of GENERAL_CONF register 0x00).
 Set proper CLK_GATING_DELAY register 0x14.
 Set CLK_GATING_REG = 0x7 (bit2:0 of register 0x4F).
Result:
When writing to CLK_GATING_REG , this activates the CLK_GATING_DELAY counter,
which specifies the delay between clock gating trigger and activation in
[number of cycles]. When the counter reaches 0, clock gating is activated. See figure
below.
NOTE :
 In case CLK_GATING_REG = 0, clock gating is executed immediately after
activating the CLK_GATING_REG register. See figure below.
In order to conduct clock gating wake-up, do as follows:
Action:
 Set STPIN input pin to high voltage level.
Result:
Clock-gating is terminated. See figure below.
If SPI datagram transfers from microcontroller to TMC4361A prompt wake-
up, do as follows:
Action:
 Set CLK_GATING_DELAY = 0xFFFFFFFF (register 0x14).
 Set CLK_GATING_REG = 0x0 (bit2:0 of register 0x4F).
 Set CLK_GATING_REG = 0x7 (bit2:0 of register 0x4F).
 Set clk_gating_en = 0 (bit17 of GENERAL_CONF register 0x00).
Result:
Clock-gating is terminated.
Figure 70: Manual Clock Gating Activation and Wake-Up
External
clk signal
Internal clk
signal
CLK_GATING_REG
=111
CLK_GATING_DELAY
=5
CLK_GATING_REG
=111
SPI
Inputs
Clock gating
delay timer
STPIN input signal
Activating Clock
Gating manually
Clock Gating
Wake-up