Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
SPI Encoder Data Evaluation
SPI encoder interfaces typically consist of four signal lines. In addition to SSI encoder signal
lines (SCLK, MISO), a chip select line (CS) and a data input (MOSI) to the master is provided.
The number of bits per transfer is calculated automatically; based on proper
multi_turn_in_en , SINGLE_TURN_RES , MULTI_TURN_RES , and STATUS_BIT_CNT , as
explained in sections 15.4.1 (page 149) and 15.4.4 (page 151).
A typical SPI communication process responds to any SPI data transfer request when
the next transmission occurs. When TMC4361A receives an answer from the encoder,
it calculates ENC_POS immediately. The encoder slave does not send any data without
receiving a request first.
Therefore, TMC4361A always sends ADDR_TO_ENC value to request encoder data
from the SPI encoder slave device. The LSB of the serial data output is
ADDR_TO_ENC (0).
Received encoder data is stored in ADDR_FROM_ENC . Thus, encoder values can be
verified and compared to microcontroller data later on.
i The clock generation works similarly to SSI clock generation, as described in
section 15.4.5 on page 153; based on proper SER_CLK_IN_HIGH, SER_PTIME,
and SER_CLK_IN_LOW .
In order to configure a basic SPI communication procedure, do as follows:
Action:
 Set SINGLE_TURN_RES ( ENC_IN_DATA register 0x08) to the number of
singleturn data bits -1.
 Set MULTI_TURN_RES ( ENC_IN_DATA register 0x08) to the number of multiturn
data bits -1 in case multiturn data is enabled and used.
 Set STATUS_BIT_CNT ( ENC_IN_DATA register 0x08) to the number of status
bits.
 Set proper left_aligned_data ( ENC_IN_CONF register 0x07).
 Set correct SPI transfer mode that is described in the next section.
 Set ADDR_TO_ENC register 0x68 to the specified SPI encoder address that
contains angle data.
 Set proper SER_CLK_IN_LOW (register 0x56) in internal clock cycles.
 Set proper SER_CLK_IN_HIGH (register 0x56) in internal clock cycles.
 OPTIONAL CONFIG: Set proper SER_PTIME (register 0x58) in internal clk
cycles.
 Finally, set serial_enc_in_mode = b’11.
Result:
TMC4361A emits serial clock streams at SCLK in order to receive absolute encoder
data at SDI pin. The number of generated clock cycles depends on
SINGLE_TURN_RES , MULTI_TURN_RES , and STATUS_BIT_CNT .
Pin ANEG_NSCLK functions as negated chip select line for the SPI encoder that is
generated according to the serial clock and the selected SPI mode; which is described
in the next section.
Pin BNEG_NSDI is the MOSI line that transfers SPI datagrams to the SPI encoder.
Datagrams, which are transferred permanently to receive angle data, consists of
ADDR_TO_ENC data.
SER_PTIME defines the interval between two consecutive data requests.
Turn page for information on SPI mode selection.
SPI Encoder
Communication
Process