Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
SSI Clock Generation
In order to receive encoder data from the absolute encoder, TMC4361A generates clock
patterns according to SSI standard. Data transfer is initiated by switching the clock line SCLK
from high to low level. The transfer starts with the next rising edge of SCLK. The number of
emitted clock cycles depends on the expected data width, as explained in section 15.4.4.
One clock cycle has a high and a low phase, which can be defined separately according
to internal clock cycles. Per default, sample points of serial data are set at the falling
edges of SCLK. Some encoders need more clock cycles – than are available during the
low clock phase – in order to prepare data for transfer. Also, due to long wires, data
transfer can take more time. To counteract the above mentioned issues, the delay
time SSI_IN_CLK_DELAY (default value equals 0) for compensation can be specified
in order to prolong the sampling start. Therefore, this delay configuration can
automatically generate more clock cycles.
After a data request – when all clock cycles have been emitted – the serial clock must
remain idle for a certain interval before the next request is automatically initiated. This
interval SER_PTIME can also be configured in internal clock cycles.
i According to SSI standard, select an interval that is longer than 21 µs.
In order to configure the SSI clock generation, do as follows:
Action:
 Set SINGLE_TURN_RES ( ENC_IN_DATA register 0x08) to the number of
singleturn data bits -1.
 Set MULTI_TURN_RES ( ENC_IN_DATA register 0x08) to the number of multiturn
data bits -1 in case multiturn data is enabled and used.
 Set STATUS_BIT_CNT ( ENC_IN_DATA reg. 0x08) to the number of status bits.
 Set proper left_aligned_data ( ENC_IN_CONF register 0x07).
 Set proper SER_CLK_IN_LOW (register 0x56) in internal clock cycles.
 Set proper SER_CLK_IN_HIGH (register 0x56) in internal clock cycles.
 OPTIONAL CONFIG: Set proper SSI_IN_CLK_DELAY (register 0x57) in internal
clock cycles.
 OPTIONAL CONFIG: Set proper SER_PTIME (reg. 0x58) in internal clk cycles.
 Finally, set serial_enc_in_mode = b’01.
Result:
TMC4361A emits serial clock streams at SCLK in order to receive absolute encoder
data at SDI. If SSI_IN_CLK_DELAY > 0, the SDI sample points are delayed (see figures
below). SER_PTIME defines the interval between two consecutive data requests.
i If differential encoder is selected, the negated clock emits at ¬SCLK; and ¬SDI
is also evaluated.
Figure 64: SSI: SSI_IN_CLK_DELAY=0
Figure 65: SSI: SSI_IN_CLK_DELAY>SER_CLK_IN_HIGH
LSBMSB
Sample points
Serial data in
Serial clock
out
SER_CLK_IN_HIGH SER_CLK_IN_LOW
MSB LSB---
Sample points
Serial data in
Serial clock
out
SSI_IN_CLK_DELAY
Configuration
Details