Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
If connected to TMC26x drivers, TMC4361A must generate the dcStep signal
internally; despite particular motor settings dcStep requires only very few settings,
which could be tunneled via SPI through TMC4361A.
dcStep directly feeds motor motion back to the ramp generator so that it becomes
seamlessly integrated into the motion ramp; even if the motor becomes overloaded
with respect to the target velocity. In order to set up the hardware correctly the
SG_TST output pin of TMC26x must be connected to the MP1 input pin of TMC4361A;
and the TST_MODE pin of TMC26x must be connected to VCCIO.
i Please also refer to the corresponding TMC26x manuals for the correct motor
driver settings.
In order to set up a TMC26x dcStep configuration, do as follows:
PRECONDITION: TMC26X MOTOR DRIVER SETUP:
 Set CHM = 1 (constant tOFF-Chopper).
 Set HSTRT = 0 (slow decay only).
 Set SGTO = 1 and SGT1 = 1 (on_state_xy as test signal output).
 Set TST = 1 (Test mode on).
Action:
 Set spi_output_format = b’1011 or b’1010 (automatic TMC26x setting)
 Set the upper PWM time DC_TIME slightly higher than the driver effective blank
time TBL (register 0x61).
 Set DC_BLKTIME [clock cycles] when no comparison should happen after a fullstep
release (register 0x61).
 Set DC_SG [clock cycles · 16] as PWM on-time for step loss detection (0x61).
 Set dcstep_mode = b’01 ( GENERAL_CONF register 0x00).
Result:
The internal dcStep at MP1 input signal approves further step generation in case the
input step signals are smaller than the DC_TIME step length in clock cycles.
NOTE:
 Even though dcStep is able to decelerate the motor during overload,
stalls can occur due to certain negative influences, such as:
The motor may stall and lose steps, e.g. because deceleration drops below
obligational minimum velocity. In order to safely detect a step loss and
avoid restarting of the motor, the stop on stall can be enabled
(see section 10.4.4, page 102).
Concerning dcStep operation with TMC26x: the stall bit from the driver
status is substituted by the dcStep stall detection bit.
Therefore, the first step at MP1 input directly after a step release is
checked against the DC_SG value, which is the maximum PWM on-time. In
case the signal step length is smaller than DC_SG, a stall has occurred.
DC_BLKTIME specifies the number of clock cycles after a fullstep release in
case nothing must be compared; because fragmented steps could occur at
MP1. The first step after release that is checked is the first step after blank
time. The switch to fullstep drive is performed automatically, as explained
in section 10.6.5 and 10.6.6, page 109).
Enabling dcStep
for TMC26x
Stepper Motor
Drivers