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Motion Controller for Stepper Motors Integrated Circuits

 SHORT SPEC 

TMC4361A DATASHEET

TMC4361A Document Revision 1.22 • 2017-JAN-12

SHORT SPEC

The S-ramp and sixPoint™ ramp motion controller for stepper motors is optimized for high

velocities, allowing on-the-fly changes. TMC4361A offers SPI and Step/Dir interfaces, as well

as an encoder interface for closed-loop operation.

NOTE:



TMC4361A is a product upgrade of TMC4361.

Features

 SPI Interfaces for µC with easy-to-use protocol.

 SPI Interfaces for SPI motor stepper drivers.

 Encoder interface for incremental or serial encoders.

 Closed-loop operation for Step and SPI drivers.

 Integrated ChopSync™ and dcStep™ support.

 Internal ramp generator generating S-shaped ramps

or sixPoint™ ramps supporting on-the-fly changes.

 Controlled PWM output.

 Reference switch handling.

 Hardware and virtual stop switches.

 Extensive Support of TMC stepper motor drivers.

Applications

 Textile, sewing machines

 CCTV, security

 Printers, scanners

 ATM, cash recycler

 Office automation

 POS

 Factory automation

 Lab automation

 Pumps and valves

 Heliostat controllers

 CNC machines

 Robotics

Block Diagram: TMC4361A Interfaces & Features

Figure 2: Block Diagram

Germany — Terms of delivery and rights to technical change

reserved. Download newest version at: www.trinamic.com.

Read entire documentation; especially the

Supplemental Directives in chapter 22 (page 224).

TMC4361

SPI to

Master

Safe Ramp Down

Status Flags

Interrupt

Controller

Ref. Switch

Processing

Driver

Interface:

SPI /

Step/Dir

Ref. Switches

S-Ramp

Generator

incl. trapezoid,

rectangle, 4bows

SPI

Step/Dir

SPI to µC

INTR / TR to µC

Timer Unit

Power-on

Reset

Step

Sequencer

Current

Regulation

Encoder

Interface

Closed Loop

ABN

SSI

SPI

NFreeze

CLK

NRST

dcStep

START

Figure 1: Sample Image

TMC4361A Closed-Loop Drive

*Marking details are explained on page 223.

Summary of content (230 pages)

PAGE 1
Motion Controller for Stepper Motors Integrated Circuits TMC4361A DATASHEET TMC4361A Document Revision 1.22 • 2017-JAN-12 SHORT SPEC The S-ramp and sixPoint™ ramp motion controller for stepper motors is optimized for high velocities, allowing on-the-fly changes. TMC4361A offers SPI and Step/Dir interfaces, as well as an encoder interface for closed-loop operation. NOTE:  TMC4361A is a product upgrade of TMC4361.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 2/230 Functional Scope of TMC4361A TMC4361A is a miniaturized high-performance motion controller for stepper motor drivers, particularly designed for fast and jerk-limited motion profile applications with a wide range of ramp profiles.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 3/230 T A BL E O F C O NT E NT S TMC4361A DATASHEET .................................................................................................... 1 SHORT SPEC ..................................................................................................................... 1 Features ........................................................................................................................... 1 Applications ..................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 4/230 Trapezoidal Ramp with Break Point .................................................................................... 35 Position Mode combined with Trapezoidal Ramps ................................................................ 36 Configuration of S-Shaped Ramps ....................................................................................... 37 S-Ramps: Changing Ramp Parameters during Motion or Switching to Positiong Mode ........
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 5/230 9. Ramp Timing and Synchronization .......................................................................... 69 Basic Synchronization Settings ............................................................................................ 70 Start Signal Trigger Selection ............................................................................................. 70 User-specified Impact Configuration of Timing Procedure ......................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 6/230 TMC26x Setup (SPI mode) ...............................................................................................107 TMC26x Setup (S/D mode) ................................................................................................107 Sending Cover Datagrams to TMC26x ................................................................................108 Automatic Continuous Streaming of Cover Datagrams for TMC26x ....................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 7/230 15. Decoder Unit: Connecting ABN, SSI, or SPI Encoders correctly ............................. 141 Selecting the correct Encoder ............................................................................................142 Disabling digital differential Encoder Signals .......................................................................143 Inverting of Encoder Direction ....................................................................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 8/230 17. Reset and Clock Gating .......................................................................................... 169 Manual Hardware Reset ....................................................................................................169 Manual Software Reset .....................................................................................................169 Reset Indication ......................................................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 9/230 20. Absolute Maximum Ratings ................................................................................... 216 21. Electrical Characteristics........................................................................................ 217 Power Dissipation .............................................................................................................217 General IO Timing Parameters ..............................................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 10/230 M AI N MA NU AL 1. Pinning and Design-In Process Information In this chapter you are provided with a list of all pin names and a functional description of each.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 11/230 Pin Description Pin Names and Descriptions Pin Number Type Function Supply Pins GND 6, 15, 25, 36 GND Digital ground pin for IOs and digital circuitry. VCC 5, 26, 37 VCC Digital power supply for IOs and digital circuitry (3.3V… 5V). VDD1V8 16, 35 VDD Connection of internal generated core voltage of 1.8V.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 12/230 Pin Names and Descriptions Pin Number Type Function Interface Pins for Stepper Motor Drivers NSCSDRV PWMB SDO 30 O Low active chip selects output of SPI interface to motor driver. Second PWM signal (Cosine) to connect with PHB (TMC23x/24x). Serial data output of serial encoder output interface. SCKDRV MDBN NSDO 29 O Serial clock output of SPI interface to motor driver. MDBN output signal for MDBN pin of TMC23x/24x.
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TMC4361A Datasheet | Document Revision 1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 2. 14/230 Application Circuits In this chapter application circuit examples are provided that show how external components can be connected. TMC4361A Standard Connection: VCC=3.
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TMC4361A Datasheet | Document Revision 1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 3. 16/230 SPI Interfacing TMC4361A uses 40-bit SPI datagrams for communication with a microcontroller. The bit-serial interface is synchronous to a bus clock. For every bit sent from the bus master to the bus slave, another bit is sent simultaneously from the slave to the master. In the following chapter information is provided about the SPI control interface, SPI datagram structure and SPI transaction process.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Read/Write Selection Principles and Process 17/230 Read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram). This bit is 0 for read access and 1 for write access. Consequently, the bit named W is a WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. Consequently, 0x80 must be added to the address for a write access.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 18/230 Data Alignment All data is right-aligned. Some registers represent unsigned (positive) values; others represent integer values (signed) as two’s complement numbers. Some registers consist of switches that are represented as bits or bit vectors.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 19/230 SPI Timing Description The SPI interface is synchronized to the internal system clock, which limits SPI bus clock SCKIN to a quarter of the system clock frequency. The signal processing of SPI inputs is supported with internal Schmitt Trigger, but not with RC elements. NOTE:  In order to avoid glitches at the inputs of the SPI interface between µC and TMC4361A, external RC elements have to be provided.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 4. 20/230 Input Filtering Input signals can be noisy due to long cables and circuit paths. To prevent jamming, every input pin provides a Schmitt trigger. Additionally, several signals are passed through a digital filter. Particular input pins are separated into four filtering groups. Each group can be programmed individually according to its filter characteristics.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Input Sample Rate (SR) 21/230 Input sample rate = fCLK 1/2SR where: SR i (extended with a particular name extension) is in [0… 7]. This means that the next input value is considered after 2SR clock cycles.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 22/230 Input Filtering Examples The following three examples depict input pin filtering of three different input filtering groups. i After passing Schmitt trigger, voltage levels are compared to internal signals, which are processed by the motion controller. i The sample points are depicted as green dashed lines. Example 1: Reference Input Pins In this example every second clock cycle is sampled.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 23/230 Configuration of Step/Dir Input Filter Step/Dir input filtering setup differs slightly from the other groups, because the other four groups already complete the whole INPUT_FILT_CONF register 0x03. This is why it is possible to assign the Step/Dir input group to one of the existing groups by setting the appropriate bit in front of the setup parameters.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 5. 24/230 Status Flags and Events TMC4361A provides 32 status flags and 32 status events to obtain short information on the internal status or motor driver status. These flags and events can be read out from dedicated registers. In the following chapter, you are informed about the generation of interrupts based on status events. Status events can also be assigned to the first eight SPI status bits, which are sent within each SPI datagram.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 25/230 Status Event Description Status events are based on status bits. If the status bits change, related events are triggered from inactive to active level. Resetting events back to inactive must be carried out manually.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 26/230 SPI Status Bit Transfer Up to eight events can be selected for permanent SPI status report. Consequently, these events are always transferred at the most significant transfer bits within each TMC4361A SPI response.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 27/230 Connection of Multiple INTR Pins INTR pin can be configured for a shared interrupt signal line of several TMC4361A interrupt signals to the microcontroller. Connecting several Interrupt Pins In order to make use of a Wired-Or or Wired-And behavior, the below described actions must be taken: Action:  Step 1: Set intr_tr_pu_pd_en = 1 (GENERAL_CONF register 0x00).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 6. 28/230 Ramp Configurations for different Motion Profiles Step generation is one of the main tasks of a stepper motor motion controller. The internal ramp generator of TMC4361A provides several step generation configurations with different motion profiles. They can be configured in combination with the velocity or positioning mode. Pin Names: Ramp Generator Pin Names Type Remarks STPOUT_PWMA Output Step output signal.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 29/230 Step/Dir Output Configuration This section focuses on the description of the Step/Dir output configuration. Step/Dir output signals can be configured for the driver circuit. Step/Dir Output Configuration Steps If step signals must be longer than one clock cycle, do as follows: Action:  Set proper STP_LENGTH_ADD register 0x10 (bit 15:0). Result: The resulting step length is equal to STP_LENGTH_ADD+1 clock cycles.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 30/230 Altering the Internal Motion Direction Per default, a positive internal velocity VACTUAL results in a forward motion through internal SinLUT. Consequently, if VACTUAL < 0, the SinLUT values are developed backwards. How to change Motion Direction In order to alter the default setting of the Internal Motion Direction, do as follows: Action:  Set reverse_motor_dir =1 (bit28 of GENERAL_CONF register 0x00).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 31/230 Configuration Details for Operation Modes and Motion Profiles This section provides information on the two available operation modes (velocity mode and positioning mode), and on the four possible motion profiles (no ramp, trapezoidal ramp including sixPoint™ ramp, and S-shaped ramp). Different combinations are possible. Each one of them has specific advantages.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 32/230 Starting Point: Choose Operation Mode Two operation modes are available: velocity mode and positioning mode. BEFORE YOU BEGIN ! Before setting any parameters: First select:  Operation mode and  Motion profile It is not advisable to change operation mode nor motion profile during motion. Operation Mode: Velocity Mode The RAMPMODE register provides a choice of two operation modes. Either velocity mode or positioning mode can be chosen.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Motion Profile Configuration 33/230 Three basic motion profiles are provided. Each one of them has a different velocity value development during the drive. See table below. For configuration of the motion profiles, do as follows: Action:  Use the bits 1 and 0 of the RAMPMODE register 0x20. Result: As specified in the table below.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 34/230 v(t) No Ramp Motion Profile VMAX t Figure 19: No Ramp Motion Profile In order to make use of the no ramp motion profile, which is rectangular, do as follows: Action:  Set RAMPMODE(1:0) =b’00 (register 0x20).  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is immediately set to VMAX.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 35/230 In order to make use of a trapezoidal 4-point ramp motion profile without break velocity, do as follows: Trapezoidal 4-Point Ramp without Break Point Action:  Set RAMPMODE(1:0) =b’01 (register 0x20).  Set VBREAK =0 (register 0x27).  Set proper AMAX register 0x28 and DMAX register 0x29.  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is changed successively to VMAX with a linear ramp.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Position Mode combined with Trapezoidal Ramps 36/230 Motion direction depends on XTARGET. In order to use a 4-point or sixPoint ramps during positioning mode, do as follows: Action:  Set RAMPMODE(2:0) =b’101 (register 0x20).  Set Trapezoidal ramp type accordingly, as explained above.  Set proper XTARGET register 0x37. Result: The ramp finishes exactly at the |VACTUAL| = VMAX as long as possible.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 37/230 In order to make use of S-shaped ramps, do as follows: Configuration of S-Shaped Ramps Action:  Set RAMPMODE(1:0)=b’10 (register 0x20).  Set proper BOW1 … BOW4 registers 0x2C…0x30.  Set proper AMAX register 0x28 and DMAX register 0x29.  Set ASTART = 0 (register 0x2A).  Set DFINAL = 0 (register 0x2B).  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is changed successively to VMAX with S-shaped ramps.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 38/230 Changing ramp parameters1 and/or operation mode during motion is not advised. However, if this is necessary, the following applies: Avoid unintended system behavior during positioning mode! Ramp parameter value changes during ramp progress can lead to: NOTICE   A temporary overshooting of XTARGET or mechanical stop positions.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12   Definitions for S-shaped Ramps AACTUAL 39/230   The acceleration/deceleration values are altered, based on the bow values. The start phase and the end phase of an S-shaped ramp is accelerated/decelerated by ASTART and DFINAL. The ramp starts with ASTART and stops with DFINAL. DFINAL becomes valid when AACTUAL reaches the chosen DFINAL value. i The parameter DFINAL is not considered during positioning mode.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 40/230 Start Velocity VSTART and Stop Velocity VSTOP S-shaped and trapezoidal velocity ramps can be configured with unsigned start and stop velocity values: VSTART, or VSTOP. Per default, VSTART and VSTOP are set to 0. The sign is selected automatically, depending on the current ramp status and the target velocity, or target position. This section explains how to set up the respective values correctly.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with initial Start Velocity 41/230 In order to use S-shaped ramps with initial start velocity, do as follows: Action:     Set Set Set Set RAMPMODE(1:0)=b’10 (register 0x20). S-shaped ramp type accordingly, as explained before. proper VSTART > 0 (register 0x25). VSTOP = 0 (register 0x26). Result: The S-shaped ramp starts with initial velocity. PRINCIPLE:  The initial acceleration value is equal to AMAX.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Finishing Ramps with Stop Velocity 42/230 S-shaped and trapezoidal velocity ramps can be finished with a stop velocity value if you set VSTOP value higher than zero (see figure below). In order to configure trapezoidal ramps with stop velocity, do as follows: Action:  Set RAMPMODE(1:0)=b’01 (register 0x20).  Set Trapezoidal ramp type accordingly, as explained before.  Set VSTART = 0 (register 0x25).  Set proper VSTOP > 0 (register 0x26).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with Stop Velocity 43/230 In order to use S-shaped ramps with stop velocity, do as follows: Action:  Set RAMPMODE(1:0)=b’10 (register 0x20).  Set S-shaped ramp type accordingly, as explained before.  Set VSTART = 0 (register 0x25).  Set proper VSTOP > 0 (register 0x26). Result: The S-shaped ramp finishes with stop velocity. NOTE:  The final deceleration value is equal to DMAX. The parameter DFINAL is not considered.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with Start and Stop Velocity 44/230 S-shaped ramps can be configured with a combination of VSTART and VSTOP. It is possible to include both processes in one S-Shaped ramp to decrease the time between start and stop of the ramp. In order to use S-Shaped ramps with a combination of start and stop velocity, do as follows: Action:     Set RAMPMODE(1:0)=b’10.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Combined Use of VSTART and ASTART for S-shaped Ramps 45/230 For some S-shaped ramp applications it can be useful to start with a defined velocity value (VSTART > 0);but not with the maximum acceleration value AMAX. In order to start with a defined velocity value, do as follows: Action:  Set RAMPMODE(1:0) =b’10 (register 0x20).  Set S-shaped ramp type accordingly, as explained before.  Set proper VSTART > 0 (register 0x25).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 46/230 sixPoint Ramps sixPoint ramps are trapezoidal ramps with initial and stop velocity values that also make use of two acceleration and two deceleration values. Configuration of sixPoint Ramps sixPoint ramps are trapezoidal velocity ramps that can be configured with a combination of VSTART and VSTOP.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 47/230 U-Turn Behavior The process that is triggered when motion direction changes during motion, is described below, and applies to all ramp types. U-Turn Behavior In case the motion direction is changed during motion in velocity mode (by direct assignment of VMAX) or in positioning mode (due to XTARGET reassignment), the following process is triggered: 1. Motion is directed to VACTUAL = 0. i 2.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Example: U-Turn for S-shaped Ramps 48/230 When VACTUAL = 0 is reached, motion immediately continues. In most S-shaped ramp applications that do not use VSTOP, a standstill phase is not required. If ASTART > 0 and/or DFINAL > 0, these parameters are also used during U-Turn.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 49/230 Internal Ramp Generator Units This section provides information about the arithmetical units of the ramp parameters. Clock Frequency Velocity Value Units All parameter units are real arithmetical units. Therefore, it is necessary to set the CLK_FREQ register 0x31 to proper [Hz] value, which is defined by the external clock frequency fCLK. Any value between fCLK = 4.2 MHz and 32 MHz can be selected. Default configuration is 16 MHz.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 50/230 Bow values BOW1…BOW4: Bow values are unsigned 24-bit values without decimal places. They are defined per default as pulses per second³ [pps³].
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 7. 51/230 External Step Control and Electronic Gearing Steps can also be generated by external steps that are manipulated internally by an electronic gearing process. In the following chapter, steps generation by external control and electronic gearing is presented. Pins for External Step Control Pin Names Type Remarks STPIN Input Step input signal. DIRIN Input Direction input signal.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Selecting the Input Direction Polarity 52/230 DIRIN polarity can be assigned. Per default, the negative direction is indicated by DIRIN = 0. In order to change this polarity: Action:  Set pol_dir_in = 1 (GENERAL_CONF register 0x00). Result: A negative input direction is assigned by DIRIN = 1. Description of Electronic Gearing If an external step is not congruent with an internal step, the GEAR_RATIO register 0x12 must be set accordingly.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Switching from External to Internal Control 53/230 In some cases, it is useful to switch from external to internal ramp generation during motion. TMC4361A supports a smooth transfer from direct external control to an internal ramp. The only parameter you need to know and apply is the current velocity when the switching occurs.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 8. 54/230 Reference Switches The reference input signals of the TMC4361A function partly as safety features. The TMC4361A provides a range of reference switch settings that can be configured for many different applications. The TMC4361A offers two hardware switches (STOPL, STOPR) and two additional virtual stop switches (VIRT_STOP_LEFT, VIRT_STOP_RIGHT). A home reference switch HOME_REF is also available.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 55/230 Hardware Switch Support The TMC4361A offers two hardware switches that can be configured according to your design. STOPL and STOPR The hardware provides a left and a right stop in order to stop the drive immediately in case one of them is triggered. Therefore, pin 12 and pin 14 of the motion controller must be used. NOTE:  Both switches must be enabled before motion occurs.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 How Active Stops are indicated and reset to Free Motion 56/230 When an enabled stop switch becomes active the related status flag is set in the STATUS flags register 0x0F. The flag remains active as long as the stop switch remains active. The particular event is also released in the EVENTS register 0x0E, which remains active until the event bit is reset manually.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 57/230 Virtual Stop Switches TMC4361A provides additional virtual limits; which trigger stop slopes in case the specific virtual stop switch microstep position is reached. Virtual stop positions are assigned using the VIRTUAL_STOP_LEFT register 0x33 and VIRTUAL_STOP_RIGHT register 0x34. In this section, configuration details for virtual stop switches are provided for various design-in purposes.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 How Active Virtual Stops are indicated and reset to Free Motion 58/230 At the same time when an enabled virtual stop switch becomes active the related status flag is activated in the STATUS flags register 0x0F. The flag remains active as long as the stop switch remains active. The particular event is also released in the EVENTS register 0x0E, which remains active until the event is reset manually.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 59/230 Home Reference Configuration In this section home reference switch handling is explained with information about home tracking modes, possible home event configurations and home event monitoring. For monitoring, the switch reference input HOME_REF is provided. Switch Reference Input HOME_REF Perform the following to initiate the homing process: Action:  Assign a ramp according to your needs for the homing process.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 60/230 HOME_REF Monitoring An error flag HOME_ERROR_F is permanently evaluated. This error flag indicates whether the current voltage level of the HOME_REF reference input is valid in regard to X_HOME and the selected home_event. Defining a Home Range around HOME_REF In order to avoid false error flags (HOME_ERROR_F) because of mechanical inaccuracies, it is possible to setup an uncertainty home range around X_HOME.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 61/230 STOPL and STOPR inputs can also be used as HOME_REF inputs. Homing with STOPL or STOPR OPTION 1: STOPL IS THE HOME SWITCH Action:  Set stop_left_is_home = 1 (REFERENCE_CONF register 0x01). Result: The stop event at STOPL only occurs when the home range is crossed after STOPL becomes active. The home range is given by X_HOME and HOME_SAFETY_MARGIN.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 62/230 Target Reached / Position Comparison In this section, TARGET_REACHED output pin configuration options are explained, as well as different ways how to compare different values internally. Target Reached Output Pin TARGET_REACHED output pin forwards the TARGET_REACHED_Flag. As soon as XACTUAL equals XTARGET, TARGET_REACHED is active. Per default, the TARGET_REACHED pin is high active.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 63/230 Use of TARGET_REACHED Output Per default, TARGET_REACHED pin forwards the TARGET_REACHED_Flag that signifies XACTUAL = XTARGET. The pin can also be used to forward three other flags: VELOCITY_REACHED_Flag, ENC_FAIL_Flag, POS_COMP_REACHED_Flag. NOTE:  Only one option can be selected. Four Options for TARGET_REACHED The TARGET_REACHED output REFERENCE_CONF register 0x01.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 64/230 Position Comparison of Internal Values TMC4361A provides several ways of comparing internal values. The position comparison process is permanently active and associated with one flag and one event. A positive comparison result can be forwarded through the INTR pin using the POS_COMP_REACHED event as interrupt source or by using the TARGET_REACHED pin as explained in section 8.4.2, page 63.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 65/230 Repetitive and Circular Motion TMC4361A also provides options for auto-repetitive or auto-circular motion. In this section configuration options are explained. Repetitive Motion to XTARGET Per default, reaching XTARGET in positioning mode finishes a positioning ramp. In order to continuously repeat the specified ramp, do as follows: PRECONDITION:  Set RAMPMODE(2) = 1 (positioning mode is active).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Uneven or Noninteger Microsteps per Revolution Due to definition of the limitation range, one revolution only consists of an even number of microsteps. TMC4361A provides an option to overcome this limitation.     Example 1: Uneven Number of Microsteps per Revolution 66/230 Some applications demand different requirements because a revolution consists of an uneven or noninteger number of microsteps.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Release of the Revolution Counter 67/230 By overstepping the position overflow, the internal REV_CNT register is increased by one revolution as soon as XACTUAL oversteps from (X_RANGE – 1) to -X_RANGE or is decreased by one revolution as soon as XACTUAL oversteps in the opposite direction. The information about the number of revolutions can be obtained by reading out register 0x36, which by default is the X_LATCH register (read only).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Blocking Zone Definition 68/230 The following positions are located within the blocking zone: XACTUAL ≤ VIRT_STOP_LEFT AND / OR XACTUAL ≥ VIRT_STOP_RIGHT NOTE:  In case VIRTUAL_STOP_LEFT < VIRTUAL_STOP_RIGHT, one of these conditions must be met in order to be located inside the blocking zone.  In case VIRTUAL_STOP_LEFT > VIRTUAL_STOP_RIGHT, both conditions must be met in order to be located inside the blocking zone.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 9. 69/230 Ramp Timing and Synchronization TMC4361A provides various options to initiate a new ramp. By default, every external register change is assigned immediately to the internal registers via an SPI input. With a proper start configuration, ramp sequences can be programmed without any intervention in between. Synchronization Opportunities Three levels of ramp start complexity are available.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 70/230 Basic Synchronization Settings Usually, a ramp can be initiated internally or externally. Note that a start trigger is not the start signal itself but the transition slope to the active start state. After a defined delay, the internal start signal is generated. Start Signal Trigger Selection For ramp start configuration, consider the following steps: Action:  Choose internal or external start trigger(s).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 71/230 Per default, the trigger is closely followed by the internal start signal. Delay Definition between Trigger and internally generated Start Signal In order to delay the generation of the internal start signal, do the following: Action:  Set START_DELAY register 0x13 according to your specification. Result: When a start trigger is recognized, the internal start signal is generated after START_DELAY clock cycles.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 72/230 The following three examples depict SPI datagrams, internal and external signal levels, corresponding velocity ramps, and additional explanations. SPI data is transferred internally at the end of each datagram. Ramp Timing Examples Ramp Timing Example 1 In this example, the velocity value change is executed immediately.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Ramp Timing Example 2 73/230 In this example, the velocity value and the ramp mode value change is executed after the first start signal.   Process Description The new ramp mode becomes positioning mode with S-shaped ramps. The ramp then stops at target position XTARGET because of the ramp mode change. A further XTARGET change starts the ramp again.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Ramp Timing Example 3 74/230 In this example external start signal triggers are prioritized by making use of START_DELAY > 0 and simultaneously setting immediate_start_in to 1.  Process Description  When XACTUAL equals POSCOMP the start timer is activated and the external start signal in between is ignored. The second start event is triggered by an external start signal. The POSCOMP_REACHED event is ignored.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 75/230 Shadow Register Settings Some applications require a complete new ramp parameter set for a specific ramp situation / point in time. TMC4361A provides up to 14 shadow registers, which are loaded into the corresponding ramp parameter registers after an internal start signal is generated.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Shadow Register Configuration Options Option 1: Shadow Default Configuration 76/230 Four different optional shadow register assignments are available to match the shadow register set according to your selected ramp type. The available options are described on the next pages. Please note that the only difference between the configuration of shadow option 3 and 4 is that VSTART is exchanged by VSTOP for the transfer of the shadow registers.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 2: Double-stage Shadow Register Set for S-shaped Ramps 77/230 In case S-shaped ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for S-shaped ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for S-shaped ramps, do as follows: Action:  Set shadow_option = b’01 (START_CONF register 0x02).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 3: Double-stage Shadow Register Set for Trapezoidal Ramps (VSTART) 78/230 In case trapezoidal ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for trapezoidal ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for trapezoidal ramps, do as follows: Action:  Set shadow_option = b’10 (START_CONF register 0x02).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 4: Double-stage Shadow Register Set for Trapezoidal Ramps (VSTOP) 79/230 In case trapezoidal ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for trapezoidal ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for trapezoidal ramps, do as follows: Action:  Set shadow_option = b’10 (START_CONF register 0x02).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 AREAS OF SPECIAL CONCERN ! Delayed Shadow Transfer 80/230 The values of ramp parameters, which are not selected by one of the four shadow options stay as originally configured, until the register is changed through an SPI write request. Also, the last stage of the shadow register pipeline retains the values until they are overwritten by an SPI write request if no cyclic shadow registers are selected.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 81/230 Pipelining Internal Parameters TMC4361A provides a target pipeline for sequencing subordinate targets in order to easily arrange a complex target structure. Configuration and Activation of Target Pipeline The different target values must be assigned to the X_PIPE0…7 register.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Using the Pipeline for different internal Registers 82/230 The TMC4361A pipeline (registers 0x38…0x3F) can be configured so that it splits up into maximal four segments.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Pipeline Mapping Overview 83/230 The pipeline_en parameter offers an open configuration for 16 different combinations of the pipeline segregation. As a result, the number of pipelines range from 0 to 4. This also has an impact on the pipeline depth. The possible options are as follows: eight stages, four stages, three stages and two stages. In the “Pipeline Mapping” table below, the allocated according to the pipeline setup.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Cyclic Pipelining 84/230 For all of the above shown configuration examples, it is possible to write back the current values of the selected registers (XTARGET, POS_COMP, GEAR_RATIO and/or GENERAL_CONF) to any of the pipeline registers of their assigned pipeline in order to generate cyclic pipelines.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 85/230 Example E: Cyclic pipelines for XTARGET and GEAR_RATIO, which have three pipeline stages each and GENERAL_CONF, which has two pipeline stages. Examples E+F: Using three Pipelines Example F: Two cyclic pipelines for XTARGET and GEAR_RATIO, which have two pipeline stages each and a noncyclic pipeline for GEAR_RATIO, which has three pipeline stages.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 86/230 Masterless Synchronization of Several Motion Controllers via START Pin START pin can also be assigned as tristate input in order to synchronize several microcontroller masterless. Activation of the Tristate START Pin In this case START is assigned as tristate. A busy state is enabled. During this busy state, START is set as output with a strongly driven inactive polarity.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 87/230 10. Serial Data Output TMC4361A provides an SPI interface for initialization and configuration of the motor driver (in addition to the Step/Dir output) before and during motor motion. It is possible to control TMC stepper drivers during SPI motor drive.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 88/230 Register Names for SPI Output Registers Register Name Register Address Remarks FREEWHEEL_DELAY 0x16 RW Delay time after freewheeling is valid. VDRV_SCALE_LIMIT 0x17 RW Velocity setting for changing the drive scale value. UP_SCALE_DELAY 0x18 RW Increment delay to a higher scaling value; 24 bits. HOLD_SCALE_DELAY 0x19 RW Decrement delay to the hold scaling value; 24 bits.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 89/230 Sine Wave Lookup Tables TMC4361A provides a programmable lookup table (LUT) for storing the current wave. Reprogramming the table from its predefined values to a motor-specific wave allows improved motor-reliant microstepping, particularly when using low-cost motors. SETTINGS ALERT ! TMC4361A-LA provides a default configuration of the internal microstep table MSLUT. In case internal MSLUT is used, proceed with section 10.3.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 90/230 Actual Current Values Output Actual Current Calculations When the microstep sequencer advances within the microstep table (MSLUT), it calculates the actual current values for the motor coils with each microstep, and stores them to the register 0x7A , which comprises the values of both waves CURRENTA and CURRENTB. However, the incremental coding requires an absolute initialization – especially when the microstep table becomes modified.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 91/230 Setup of MSLUT Segments Base Wave Inclination and Border Values All base wave inclination values (each consists of two bits) as well as the border values (each consists of eight bit) between the segments are adjustable. They are assigned by MSLUTSEL register 0x78.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 92/230 Current Waves Start Values Starting Current Values of MSLUT Configuration As both waves are shifted by 90° for two-phase stepper motors, the sine wave starts at 0° when MSCNT = 0. By comparison, the cosine wave begins at 90° when MSCNT = 256. At this starting points the current values are CURRENTA = 0 for the sine wave and CURRENTB = 247 for the cosine wave.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 93/230 Explanatory Notes for Base Wave Inclinations Definition of Segments 0,1,2,3 In the following example four segments are defined.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Standard Sine Wave Setup 94/230 In order to set up the standard sine wave table, proceed as follows: Action:  Set a starting value START_SIN = 0 matching sine wave entry 0.  Set a base wave inclination range of W0 = b’10 = 2 to skip between +1 / +2, valid from 0 to X1.  Calculate the differences between every entry: {+1, +2, +1, +2, +1, +2, +1,…}.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 95/230 SPI Output Interface Configuration Parameters TMC4361A provides an SPI output interface. In the next section, the configuration of the interface parameters is explained in detail. How to enable SPI Output Communication In order to enable SPI output communication, do as follows: Action:  Set serial_enc_out_enable = 0 (bit24 of GENERAL_CONF register 0x00). Result: SPI output is enabled.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Setup of SPI Output Timing Configuration 96/230 Because TMC4361A represents the master of SPI communication to the motor driver – which is the slave – it is mandatory to set up the timing configuration for the SPI output. TMC4361A provides an SPI clock, which is generated at the SCKDRV_NSDO output pin.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Current Diagrams Process Description Basically, SPI output communication serves as automatic current datagram transfer to the connected motor driver. TMC4361A uses the internal microstep lookup table (MSLUT) in order to provide actual current motor driver data.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Sending Cover Datagrams 98/230 The LSB (last significant bit) of the whole cover datagram register is located at COVER_LOW(0). As long as COVER_DATA_LENGTH < 33, only COVER_LOW or parts of this register are required for cover data transfer. If more than 32 bits are necessary, the complete COVER_LOW and (parts of) the COVER_HIGH register are required for SPI cover data transfer.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 99/230 Receiving Responses to Cover Datagrams Because the transfer of a cover datagram is usually accompanied by a data transfer from the motor driver, the response is stored in registers; and is thus available for the microcontroller. COVER_DRV_HIGH register 0x6F and COVER_DRV_LOW register 0x6E form this cover response register that can also comprise up to 64 bits.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 100/230 Overview: TMC Motor Driver Connections As mentioned before, TMC4361A is able to set the cover register length automatically in case a TMC motor driver is connected. Also, several additional automatic features for the SPI communication are available by selecting TMC motor drivers.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC Motor Driver Response Datagram and Status Bits 101/230 When a TMC motor driver receives a current datagram or a cover datagram that is transmitted via SPI output of TMC4361A, status data is sent back to the TMC4361A controller immediately. The response is stored in the COVER_DRV_LOW 0x6E and COVER_DRV_HIGH 0x6F registers, just like all other cover requests.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 102/230 Stall Detection and Stop-on-Stall stallGuard and stallGuard2 Functionality TMC stepper motor driver chips with stallGuard and stallGuard2 can detect stall and overload conditions based on the motor’s back-EMF without the need of a position sensor. The stall detection status is returned via SPI. For more information, refer to the AppNote “Parameterization of stallGuard2 & coolStep” that is available online at www.trinamic.com .
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 103/230 TMC23x, TMC24x Stepper Motor Driver In this chapter specific information pertaining to the setup of TMC23x and TMC24x is provided.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC23x/24x Status Bits TMC23x/24x Microsteps 104/230 TMC4361A maps the following status bits of TMC23x/24x stepper drivers – which are transferred with each SPI datagram – to the STATUS register 0x0F: Status Register Mapping for TMC23x/24x STATUS bit Status flag Description @TMC4361A @TMC23x/24x STATUS (24) UV Undervoltage flag. STATUS (25) OT Over temperature flag. STATUS (26) OTPW Temperature prewarning flag.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Mixed Decay Configuration for TMC23x/24x 105/230 TMC4361A supports the mixed decay feature for the TMC23x/24x chopper in SPI_OUT_CONF register 0x04. In order to configure mixed decay bits for TMC23x/24x, do as follows: Action:  Set mixed_decay = b’00 if mixed decay must always be deactivated.  Set mixed_decay = b’01 if mixed decay must be activated for each coil during the falling ramp of the sine curve until reaching value 0.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Using TMC24x stallGuard Characteristics 106/230 TMC24x forwards stallGuard values ={LD2&LD1&LD0} instead of one stallGuard2 status bit. These bits represent an unsigned value between 0 and 7. The lower the value is the higher the mechanical load is. TMC4361A can generate a one-bit internal stall signal by analyzing the stallGuard values.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 107/230 TMC26x Stepper Motor Driver TMC26x Stepper Motor Driver Support TMC4361A provides the following features in order to support the TMC26x motor stepper driver family well:       SPI mode that sets up current values directly. S/D mode in which the TMC26x processes S/D outputs of TMC4361A. Automatic switchover between microstep and fullstep operation for both modes. Stall detection and Stop-on-Stall behavior for both modes.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Sending Cover Datagrams to TMC26x 108/230 Based on the TMC26x settings - that were explained above - TMC4361A now sends 20-bit datagrams automatically. In order to send cover datagrams to TMC26x motor stepper drivers, do as follows: Action:  Set COVER_LOW (19:0) to the register values that need to be transferred. Result: A cover datagram is sent to the connected driver. COVER_DONE is set after data transfer.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC26x SPI Mode: Automatic Fullstep Switchover 109/230 Because SPI current data is transmitted, automatic switchover from microsteps to fullsteps and vice versa entirely depends on internal ramp velocity. In order to activate automatic switchover between microstep and fullstep operation, do as follows: Action:  Set FS_VEL register 0x60 according to the absolute velocity [pps] at which the switchover should happen.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC 26x S/D Mode: Change of Current Scaling Parameter 110/230 SPI mode-supported TMC26x drivers are automatically scaled by means of current datagrams. In order to automatically scale the current of a connected TMC26x motor stepper driver in S/D mode, TM4361A sends auto-generated cover datagrams by altering directly the CS value of the TMC26x SGCSCONF register.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 111/230 TMC389 Stepper Motor Driver Configuration for the TMC389 3--Phase Stepper Driver If a TMC389 is connected to the SPI output and a microstep resolution of 256 is set, a 3-phase stepper output for coil B can be generated. All features of TMC26x stepper motor drivers in SPI mode are also available for TMC389.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 112/230 TMC2130 Stepper Motor Driver TMC2130 Support TMC4361A provides the following features in order to support the TMC2130 motor stepper driver well:       SPI mode that sets up current values directly. S/D mode in which the TMC2130 processes S/D outputs of TMC4361A. Automatic switchover between microstep and fullstep operation for both modes. Stall detection and Stop-on-Stall behavior for both modes.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Sending Cover Datagrams to TMC2130 113/230 Based upon the TMC2130-supported settings explained above, the TMC4361A now sends 40 bit datagrams automatically. In order to send cover datagrams to TMC2130 stepper drivers, do as follows: Action:  Set COVER_HIGH (7:0) register 0x6D to address value that needs to be sent.  Set COVER_LOW (31:0) register 0x6C to data values that needs to be sent. Result: A cover datagram is sent to the connected driver.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC2130 SPI Mode: Automatic Fullstep Switchover 114/230 Because SPI current data is transmitted, the automatic switchover from microsteps to fullsteps and vice versa entirely depends on the internal ramp velocity. In order to activate automatic switchover between microstep and fullstep operation, do as follows: Action:  Set FS_VEL register 0x60 according to absolute velocity [pps] at which the switchover should happen.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC2130 Status Bits 115/230 TMC4361A maps the following status bits of TMC2130 stepper drivers – which are transferred within each SPI response – to the STATUS register 0x0F: Status Register Mapping for TMC2130 STATUS Bit @TMC4361A Status Flag @TMC2130 Description STATUS (24) SG stallGuard2™ status flag. STATUS (25) OT Over temperature flag.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 116/230 Connecting Non-TMC Stepper Motor Driver or SPI-DAC at SPI output interface TMC4361A also provides configuration data for driver chips of other companies via the cover registers. The following output format settings can be selected: Non-TMC Data Transfer Options Output Formats spi_output_format Comment SPI output off b’0000 SPI output driver pins are switched off.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 117/230 Connecting a SPI-DAC DAC Output Values Connecting a compatible SPI-DAC to SPI output pins, several possibilities are available for output configuration:    DAC Data Transfer Changing SPI Output Protocol for SPI-DAC Output of the internal SPI current values. Output of the internal current scaling value. Several SPI protocols are available.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 DAC Address Values 118/230 SPI transmission to a DAC transfers an address or a command prior to the value that must be defined. The length of the prefixed command/address can be assigned by setting DAC_CMD_LENGTH according to specification of the SPI-DAC.
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TMC4361A Datasheet | Document Revision 1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 120/230 11. Current Scaling The current values of register 0x7A – CURRENTA and CURRENTB – of the microstep lookup table (MSLUT) represent the maximum 9-bit signed values, which can be sent via the SPIOUT output interface. In most sections of the velocity ramp it is not required to drive the motor with the full current amplitude.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Hold Current Scaling 121/230 During standstill, the current can be scaled down considerably in most applications because the energy demand is lower than during motion. In addition to the scaling value, the standby delay must be configured. The delay defines the time between ramp stop and startup of hold scaling. Whenever the delay is set to 0, hold scaling is immediately enabled at the end of the velocity ramp.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 122/230 Current Scaling during Motion If the current values need to be scaled during motion, several options are available. Up to three scaling values can be selected: Two drive scaling values and one boost scale value. Different scale values can be automatically assigned to the various sections of the velocity ramp. Drive Scaling Drive scaling is the preferred direct and mostly unconditional scaling option.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Boost Current 123/230 In certain sections of the velocity ramp it can be useful to boost the current. Boost current can be assigned temporarily either after ramp start or during the whole ac-/deceleration phase. All options can be selected separately, or in combination. i All three options use the same scaling value BOOST_SCALE_VAL.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 124/230 Scale Mode Transition Process Control Transition from one scale value to the next active value can be configured as slight conversion. It is advisable to avoid abrupt scaling alterations, which can cause unwanted oscillations and/or motor stall. Three different parameters can be set to convert to higher or lower current scale values.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Transition to lower Motion Current Scaling ! 125/230 To avoid step loss or unwanted oscillations – in case a lower scale value is assigned during motion – the transition from high to low current scale values can be adapted also.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 126/230 Current Scaling Examples Scaling Mode Example 1 In this example, the following scale options are enabled:      Standby scaling Freewheeling Boost scaling at start Boost scaling on deceleration ramps Drive scaling The different scaling stages of the trapezoidal velocity ramp are shown in different colors in the Figure A below. Figure B shows the internal scale parameter SCALE_PARAM as function of time.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Scaling Mode Example 2 127/230 In this example, the following scale options are enabled:   Boost scaling on acceleration ramps Drive scaling 1 and 2 As long as |VACTUAL| < VDRV_SCALE_LIMIT, Drv1 scaling is active. Both drive scaling modes are used for the deceleration ramp because boost current is not enabled during deceleration slopes (boost_current_on_dec = 0).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 128/230 12. NFREEZE and Emergency Stop In case dysfunctions at board level occur, some applications require an additional strategy to end current operations without any delay. Therefore, TMC4361A provides the low active safety pin NFREEZE. NFREEZE is low active. An active NFREEZE input transition from high to low level stops the current ramp immediately in a user configured way.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Configuration of DFREEZE for automatic Ramp Stop 129/230 DFREEZE can be used for an automatic ramp stop configuration. Two options are available:   Option 1: Use of DFREEZE = 0 for a hard stop. Option 2: Use of DFREEZE ≠ 0 for a linear deceleration ramp.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 130/230 13. Controlled PWM Output TMC4361A offers controlled PWM (Pulse Width Modulation) signals at STPOUT and DIROUT output pins. These PWM signals can be scaled, depending on the internal velocity. If a TMC23x/24x stepper motor driver is connected and configured properly, the PWM signals are redirected to two SPI output interface pins. This avoids rerouting of signal lines at board level if SPI mode is switched to PWM mode, or vice versa.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 131/230 PWM Output Generation and Scaling Possibilities Enable PWM Output Generation The STPOUT and DIROUT output pins generally forward internal generated microsteps and motion direction. In contrast to that, it is possible to forward the internal MSLUT value as PWM output signals, which is dependent on the PWM frequency.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 PWM Scale Example 132/230 In Figure 54 below, the calculation of minimum/maximum PWM duty cycles with PWM_AMPL = 32767 is shown on the left side. Resulting duty cycles for different positions in the sine voltage curve are depicted on the right side. Calculated delays of minimum/maximum duty cycles are also shown. PWM_SCALE voltage(V) 0.5 I II (PWM_AMPL+1) 2^17 t I tDUTY_CYCLE PWM_VMAX III VACTUAL t PWM_FREQ fCLK tDUTY_MAX=(0.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 133/230 PWM Output Generation for TMC23x/24x Controlled PWM Signals for TMC23x/24x PWM output signals can be used for TMC23x/24x stepper motor drivers Voltage PWM mode. TMC4361A forwards the internal PWM output signals at the corresponding SPI output interface pins because the drivers share input and output pins for the SPI mode and the Voltage PWM mode.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Switching between SPI and Voltage PWM Modes 134/230 The hardware setup scenario, as shown on the previous page, also allows switching between SPI and Voltage PWM mode. It is advisable to enable or disable the Voltage PWM mode during standstill of the internal ramp. In order to disable Voltage PWM mode for TMC23x/24x, do as follows: Action:  Set pwm_out_en = 0 (GENERAL_CONF register 0x00).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 135/230 14. dcStep Support for TMC26x or TMC2130 dcStep is an automatic commutation mode for stepper motor drivers. It allows to run the stepper with its nominal velocity, which is generated by the internal ramp generator for as long as it can cope with the motor load. In case the motor becomes overloaded, it slows down to a lower velocity at which the motor can still drive the load.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 dcStep increases usable Motor Torque torque MMAX 136/230 In a classical application, the operation area is limited by the maximum torque required at maximum application velocity. A safety margin of up to 50% torque is required, in order to compensate unforeseen load peaks, torque loss due to resonance, and aging of mechanical components. dcStep makes it possible to use the available motor torque to its fullest.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling dcStep for TMC26x Stepper Motor Drivers 137/230 If connected to TMC26x drivers, TMC4361A must generate the dcStep signal internally; despite particular motor settings dcStep requires only very few settings, which could be tunneled via SPI through TMC4361A.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Setup: Minimum dcStep Velocity 138/230 dcStep requires a minimum operation velocity DC_VEL [pps]. DC_VEL must be set to the lowest operating velocity at which dcStep provides a reliable detection of motor operation. In case an overload appears, an internal dcStep signal is generated that pauses internal step generation. Because dcStep operates the motor in fullstep mode, a minimum fullstep frequency fFS can be assigned.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 AREAS OF SPECIAL CONCERN ! 139/230 Different chopper settings for microstep and fullstep/dcStep mode of TMC26x stepper driver can be transferred automatically during motion. Switching between dcStep mode and microstep mode often requires different chopper settings for TMC26x stepper motor drivers. It is possible to automatically transfer cover datagrams to TMC26x (see section 10.3.7, page 99).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling dcStep for TMC2130 Stepper Motor Drivers 140/230 dcStep operation with TMC2130 is similar to a handshake procedure: The MP1 input must be connected to the DCO output pin of TMC2130, whereas MP2 must be connected to the DCEN input pin of TMC2130.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 141/230 15. Decoder Unit: Connecting ABN, SSI, or SPI Encoders correctly TMC4361A is equipped with an encoder input interface for incremental ABN encoders, absolute SSI or SPI encoders. This chapter provides basic setup information for correct analysis of connected encoder signals. Decoder Pins Pin Names Type Remarks A_SCLK Input or Output ANEG_NSCLK Input or Output B_SDI Input BNEG_NSDI Input or Output N Input N signal of ABN encoder.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Selecting the correct Encoder 142/230 The encoder interface consists of six pins that can be connected with different encoder types. Depending on the encoder type, the pins serve as inputs or as outputs. If inputs are assigned, the incoming signals can be filtered, as explained in chapter 4, page 20. Consequently, SR_ENC_IN and FILT_L_ENC_IN must be set accordingly.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Disabling digital differential Encoder Signals 143/230 If incremental ABN or absolute SSI encoders are selected, the dedicated encoder signals are treated as digital differential signals per default. For internally displaying a valid input level, the levels of a dedicated pair must be digitally inversed. i No analog differential circuit is available.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 144/230 If the encoder is installed correctly, the encoder values form a circle for one motor revolution. Thus, the deviation ENC_POS_DEV between real position ENC_POS und internal position XACTUAL forms a constant function over the whole motor revolution. Consequently, the resulting form of a deficiently installed encoder is oval-shaped. This system failure results in a new function of ENC_POS_DEV that is similar to a sine function.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 145/230 Incremental ABN Encoder Settings Incremental ABN encoders increment or decrement the external position counter register ENC_POS 0x50. This is based on A- and B-signal level transitions. Automatic Constant Configuration of Incremental ABN Encoder The external position register ENC_POS 0x50 is based on internal microsteps. Thus, every AB transition is transferred to microsteps by a fixed constant value.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 146/230 Incremental Encoders: Index Signal: N resp. Z The index signal (N or Z channel) represents a recurrence of the same position in one motor encoder revolution. TMC4361A makes use of this signal to clear the external position counter, or to take a snapshot of the external or internal position, which then can be used to refine the home position more precisely.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 A and B Channel Signal Polarities for N Event 147/230 It can be useful to specify A and B channel signal polarities for N event. Per default, the polarities of both signal lines are set to 0 (low active). In order to set up A channel polarity to high active for N event, do as follows: Action:  Set pol_a_for_n = 1 (ENC_CONF register 0x07). Result: Now, A channel signal polarity for N event is high active.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Latching External Position Continous Encoder Latching 148/230 N event can be used to latch external position register ENC_POS 0x50 to storage register ENC_LATCH 0x51 (read access). Two choices are available: Continous latching and single latching. In order to continuously latch ENC_POS to ENC_LATCH on N event, do as follows: Action:  Set clr_latch_cont_on_n = 1 (ENC_CONF register 0x07).  Set latch_enc_on_n = 1 (ENC_CONF register 0x07).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 149/230 Absolute Encoder Settings Serial encoders provide absolute encoder angle data in contrast to step transitions, which are delivered from incremental encoders. TMC4361A provides an external clock for the encoder in order to trigger serial data input, Singleturn or Multiturn Data TMC4361A offers singleturn and multiturn options for the serial data stream interpretation. Per default, multiturn data is not enabled.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Automatic Constant Configuration of Absolute Encoder 150/230 The external position register ENC_POS 0x50 is based on internal microsteps. Thus, every input data angle is transferred to microsteps by a fixed constant value. TMC4361A is able to automatically calculate this constant. In order to configure the absolute encoder constant automatically, do as follows: Action:  Set fullstep resolution of the motor in FS_PER_REV (STEP_CONF register 0x0A).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Absolute Encoder Data Setup 151/230 Encoder Data must be maintained correctly. Consequently, certain settings must be configured so that TMC4361A displays them as specified. In order to configure absolute encoder data, do as follows: Action:  Set SINGLE_TURN_RES (ENC_IN_DATA register 0x08) to the number of singleturn data bits -1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Emitting Encoder Data Variation 152/230 For some applications it can be useful to limit the difference between two consecutive encoder data values; for instance, if encoder data lines are subject to too much noise. Per default, encoder data values can show a difference of 1/8th per encoder revolution, only if the limitation is enabled. The difference can be configured to a smaller value, if necessary.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 153/230 SSI Clock Generation In order to receive encoder data from the absolute encoder, TMC4361A generates clock patterns according to SSI standard. Data transfer is initiated by switching the clock line SCLK from high to low level. The transfer starts with the next rising edge of SCLK. The number of emitted clock cycles depends on the expected data width, as explained in section 15.4.4.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling Multicycle SSI request 154/230 If safe transmission must be determined, it is possible to send a second request so that the encoder repeats the same encoder data. Therefore, a second interval SSI_WTIME must be defined. i According to SSI standard, select an interval that is shorter than 19 µs. In order to enable multicycle requests, do as follows: Action:  Set ssi_multi_cycle_data =1 (ENC_IN_CONF register 0x07).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 155/230 SPI Encoder Data Evaluation SPI encoder interfaces typically consist of four signal lines. In addition to SSI encoder signal lines (SCLK, MISO), a chip select line (CS) and a data input (MOSI) to the master is provided. SPI Encoder Communication Process The number of bits per transfer is calculated automatically; based on proper multi_turn_in_en, SINGLE_TURN_RES, MULTI_TURN_RES, and STATUS_BIT_CNT, as explained in sections 15.4.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 SPI Encoder Mode Selection 156/230 Per default, SPI encoder data transfer is managed in the same way as the communication between microcontroller and TMC4361A. TMC4361A supports all four SPI modes with proper setting of switches spi_low_before_cs and spi_data_on_cs. THE PROCESS IS AS FOLLOWS: By setting spi_low_before_cs = 0, negated chip select line at ANEG_NSCLK is switched to active low before the serial clock line SCLK switches.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 157/230 SPI Encoder Configuration via TMC4361A Connected SPI encoder can be configured via TMC4361A., which renders a connection between microcontroller and encoder unnecessary. SPI Encoder Configuration Communication Process A configuration request is sent using the settings of SERIAL_ADDR_BITS and SERIAL_DATA_BITS, which define the transferring bit numbers.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 158/230 16. Possible Regulation Options with Encoder Feedback Beyond simple feedback monitoring, encoder feedback can be used for controlling motion controller outputs in such a way that the internal actual position matches or follows the real position ENC_POS. Two options are provided: PID control and closed-loop operation.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 PID-based Control of XACTUAL 159/230 Based on a position difference error PID_E = XACTUAL – ENC_POS the PID (proportional integral differential) controller calculates a signed velocity value (vPID), which is used for minimizing the position error. During this process, TMC4361A moves with vPID until |PID_E| – PID_TOLERANCE ≤ 0 is reached and the position error is removed.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 PID Control Parameters and Clipping Values 160/230 In order to set parameters and clipping values for PID regulation correctly, consider the following details: PID_DV_CLIP 0x5E Large velocity variations are avoided by limiting vPID value with PID_DV_CLIP (register 0x5E). This clipping parameter limits both vPID and PID_VEL. PID_I_CLIP 0x5D (14:0) The error sum PID_ISUM (read out at 0x5B) is generated by the integral term.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 161/230 Closed-Loop Operation The closed-loop unit of TMC4361A directly modifies output currents and Step/Dir outputs of the internal step generator; which is dependent on the feedback data. The 2-phase closed-loop control of TMC4361 follows a different approach than Field-Oriented Control (FOC); which is similar to PID control cascades.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 163/230 In order to limit catch-up velocities in case a disturbance of regular motor motion must be compensated, the following parameters can be configured accordingly: Limiting Closed-Loop Catch-Up Velocity i Refer to section 16.2. on page 159 for more information about PI regulation of the maximum velocity because it uses the same PI regulator like the position PID regulator. The base velocity is the actual ramp velocity VACTUAL.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling ClosedLoop Velocity Mode 164/230 Some applications only require maintaining a specified velocity value during closedloop behavior, regardless of position mismatches. TMC4361A also provides this option. NOTE:  The closed-loop velocity mode is set independent of the internal ramp operation mode (velocity or positioning mode).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 165/230 Closed-loop Scaling In order to save energy, current scaling can be adjusted according to actual load during closedloop operation. Closed-Loop Scaling Configuration and Enabling Closed-loop scaling slightly alters the use of the scaling register while remaining consistent in its use of internal scaling and the transmission to the stepper drivers: 1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Closed-Loop Scaling Transition Process Control 166/230 Transition from one scale value to the next active value can be configured as slight conversion. Two different parameters can be set in order to convert to higher or lower closed-loop current scale values, as depicted in the chart below.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 167/230 Back-EMF Compensation during Closed-loop Operation When higher velocities are reached, a phase shift between current and voltage occurs at the motor coils. Consequently, current control is transformed into voltage control. This motor- and setup-dependent effect must be compensated because currents are still continuously assigned for motor control.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 168/230 Encoder Velocity Readout Parameters In case an encoder is connected, REAL motor velocity can be read out. The actual encoder velocity flickers. This is system-immanent. TMC4361A provides filter options that back-EMF compensation is based on. The following velocity parameters can be read out. V_ENC 0x65 Actual encoder velocity in pulses (microsteps) per second [pps].
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 169/230 17. Reset and Clock Gating In addition to the hardware reset pin NRST and the automatic Power-on-Reset procedure, TMC4361A provides a software reset option. If not in operation, clock gating can be used to reduce power consumption. Reset and Clock Pins Pin Names Types Remarks NRST Input Low active hardware reset. STPIN Input High active wake-up signal. CLK_EXT Input Connected external clock signal.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Activating Clock Gating manually 170/230 Clock gating must be enabled before activation. In addition, the delay between activation and the active clock gating phase can be configured. In order to activate clock gating manually, do as follows: PRECONDITION: VEL_STATE_F = “00” INDICATING THAT VACTUAL = 0. Action:  Set clk_gating_en = 1 (bit17 of GENERAL_CONF register 0x00).  Set proper CLK_GATING_DELAY register 0x14.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 171/230 It is possible to use TMC4361A standby phase to automatically activate clock gating. Automatic Clock Gating Procedure i For further information about standby timer, see section 11.1. , page 121. In order to activate automatic clock gating, do as follows: Action:  Set the time frame for STDBY_DEALY register 0x15 after ramp stop, and before standby phase starts.  Set hold_current_scale_en = 1 (CURRENT_CONF register 0x05).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 172/230 18. Serial Encoder Output TMC4361A provides an option to render internal encoder data into absolute SSI encoder data. This encoder data is streamed via the SPI output interface. Pin Names for SPI Motor Drive Pin Names Type Remarks NSCSDRV_SDO Output Serial data output. SCKDRV_NSDO Output Negated serial data output. SDODRV_SCLK InOut as Input Serial clock input. SDIDRV_NSCLK Input Negated serial clock input.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 173/230 The internal [microstep] value of the external position ENC_POS 0x50 can be transferred to a serial data stream using the SPI output interface. SSI output format and structure can be configured freely. Configuration and Enabling of SSI Output Interface In order to provide SSI output data at the SPI output interface, do as follows: Action:  Set encoder resolution in register ENC_OUT_RES 0x55 (write access).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Disabling differential Encoder Output Signals 174/230 Regular SSI operation makes use differential signals. Thus, TMC4361A expects digital differential serial clock input signals. In order to disable the digital differential output signals, do as follows: Action:  Set serial_enc_out_diff_disable = 1 (Bit25 of GENERAL_CONF register 0x00). Result: Dedicated encoder signals are treated as single signals and every negated pin is ignored.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 175/230 T E C H NI C A L S P E C I F I C AT I O NS 19. Complete Register and Switches List General Configuration Register GENERAL_CONF 0x00 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks use_astart_and_vstart 0 (only valid for S-shaped ramps) 0 Sets AACTUAL = AMAX or –AMAX at ramp start and in the case of VSTART ≠ 0. 1 Sets AACTUAL = ASTART or –ASTART at ramp start and in the case of VSTART ≠ 0.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 176/230 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks serial_enc_in_mode 11:10 0 An incremental encoder is connected to encoder interface. 1 An absolute SSI encoder is connected to encoder interface. 2 Reserved 3 An absolute SPI encoder is connected to encoder interface. diff_enc_in_disable 12 0 Differential encoder interface inputs enabled.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 177/230 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks dcstep_mode 22:21 0 dcStep is disabled. 1 dcStep signal generation will be selected automatically 2 dcStep with external STEP_READY signal generation (TMC2130). 3 dcStep with internal STEP_READY signal generation (TMC26x). i TMC26x config: use const_toff-Chopper (CHM = 1); slow decay only (HSTRRT = 0); TST = 1 and SGT0=SGT1=1 (on_state_xy).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 178/230 Reference Switch Configuration Register REFERENCE_CONF 0x01 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks stop_left_en 0 0 STOPL signal processing disabled. 1 STOPL signal processing enabled. stop_right_en 1 0 STOPR signal processing disabled. 1 STOPR signal processing enabled. pol_stop_left 2 0 STOPL input signal is low active. 1 STOPL input signal is high active.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 179/230 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks latch_x_on_inactive_r 12 0 No latch of XACTUAL if STOPR becomes inactive. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes inactive. latch_x_on_active_r 13 0 No latch of XACTUAL if STOPR becomes active. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes active. stop_left_is_home 14 0 STOPL input signal is not also the HOME position.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 180/230 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks pos_comp_output 24:23 0 TARGET_REACHED is set active on TARGET_REACHED_Flag. 1 TARGET_REACHED is set active on VELOCITY_REACHED_Flag. 2 TARGET_REACHED is set active on ENC_FAIL flag. 3 TARGET_REACHED triggers on POSCOMP_REACHED_Flag. pos_comp_source 25 0 POS_COMP is compared to internal position XACTUAL.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 181/230 Start Switch Configuration Register START_CONF 0x02 START_CONF 0x02 (Default value: 0x00000000) R/W Bit Val Remarks start_en xxxx1 Alteration of XTARGET value requires distinct start signal. 4:0 xxx1x Alteration of VMAX value requires distinct start signal. xx1xx Alteration of RAMPMODE value requires distinct start signal. x1xxx Alteration of GEAR_RATIO value requires distinct start signal. 1xxxx Shadow Register Feature Set is enabled.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 182/230 START_CONF 0x02 (Default value: 0x00000000) R/W Bit Val Remarks cyclic_shadow_regs 18 19 0 Current ramp parameters are not written back to the shadow register. 1 Current ramp parameters are written back to the appropriate shadow register. Reserved. Set to 0. SHADOW_MISS_CNT 23:20 U Number of unused start internal start signals between two consecutive shadow register transfers.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 183/230 Input Filter Configuration Register INPUT_FILT_CONF 0x03 INPUT_FILT_CONF 0x03 (Default value: 0x00000000) R/W Bit Val Remarks SR_ENC_IN 2:0 3 U Input sample rate = fclk / 2SR_ENC_IN for the following pins: A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG Reserved. Set to 0. FILT_L_ENC_IN 6:4 U Filter length for these pins: A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 184/230 SPI Output Configuration Register SPI_OUT_CONF 0x04 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks spi_output_format 0 1 2 3 4 3:0 5 6 SPI output interface is connected with a SPI-DAC. SPI output values are mapped to full amplitude: Current=0  VCC/2 Current=-max  0 Current=max  VCC SPI output interface is connected with a SPI-DAC. SPI output values are absolute values.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 185/230 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks mixed_decay 5:4 (TMC23x/24x only) 0 Both mixed decay bits are always off. 1 Mixed decay bits are on during falling ramps until reaching a current value of 0. 2 Mixed decay bits are always on, except during standstill. 3 Mixed decay bits are always on. stdby_on_stall_for_24x 6 (TMC24x only) 0 No standby datagram is sent.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 186/230 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks sck_low_before_csn 4 (No TMC driver) 0 NSCSDRV_SDO is tied low before SCKDRV_NSDO to initiate a new data transfer. 1 SCKDRV_NSDO is tied low before NSCSDRV_SDO to initiate a new data transfer. new_out_bit_at_rise 5 RW 11:7 12 (No TMC driver) 0 New value bit at SDODRV_SCLK is assigned at falling edge of SCKDRV_NSDO.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Current Scaling Configuration Register CURRENT_CONF 0x05 CURRENT_CONF 0x05 (Default: 0x00000000) R/W Bit Val Remarks hold_current_scale_en 0 0 No hold current scaling during standstill phase. 1 Hold current scaling during standstill phase. drive_current_scale_en 1 0 No drive current scaling during motion. 1 Drive current scaling during motion. boost_current_on_acc_en 2 0 No boost current scaling for deceleration ramps.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 188/230 Current Scale Values Register SCALE_VALUES 0x06 SCALE_VALUES 0x06 (Default: 0xFFFFFFFF) R/W RW Bit Val 7:0 U 15:8 U 23:16 U Scaling Value Name BOOST_SCALE_VAL Open-loop boost scaling value. CL_IMIN Closed-loop minimum scaling value. DRV1_SCALE_VAL Open-loop first drive scaling value. CL_IMAX Closed-loop maximum scaling value. DRV2_SCALE_VAL Open-loop second drive scaling value.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 189/230 Various Scaling Configuration Registers Various Scaling Configuration Registers R/W Addr Bit 0x15 31:0 Val Description STDBY_DELAY (Default:0x00000000) U Delay time [# clock cycles] between ramp stop and activating standby phase. FREEWHEEL_DELAY (Default:0x00000000) 0x16 31:0 U Delay time [# clock cycles] between initialization of active standby phase and freewheeling initialization.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Encoder Signal Configuration (0x07) ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description enc_sel_decimal 0 0 Encoder constant represents a binary number. 1 Encoder constant represents a decimal number (for ABN only). clear_on_n 0 1 ENC_POS is not set to ENC_RESET_VAL. ENC_POS is set to ENC_RESET_VAL on every N event in case clr_latch_cont_on_n=1, or on the next N event in case clr_latch_once_on_n=1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 191/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description latch_enc_on_n 10 0 1 ENC_POS is not latched. ENC_POS is latched to ENC_LATCH on every N event on the next N event in case clr_latch_cont_on_n=1, or in case clr_latch_once_on_n=1. latch_x_on_n 11 0 1 XACTUAL is not latched. XACTUAL is latched to X_LATCH on every N event on the next N event in case clr_latch_cont_on_n=1, or in case clr_latch_once_on_n=1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 192/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description spi_data_on_cs 20 (SPI encoder only) 0 BNEG_NSDI provides serial output data at next serial clock line (A_SCLK) transition. 1 BNEG_NSDI provides serial output data immediately in case negated chip select line ANEG_NSCLK switches to low level.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 193/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description enc_out_gray 30 (Serial encoder output only) 0 SSI output data is binary-encoded. 1 SSI output data is gray-encoded. no_enc_vel_preproc RW 31 (Incremental ABN encoder) 0 AB signal is preprocessed for internal encoder velocity calculation. 1 No AB signal preprocessing. It is recommend to maintain AB preprocessing in order to filter encoder resonances.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 194/230 Serial Encoder Data Input Configuration (0x08) ENC_IN_DATA 0x08 (Default: 0x00000000) R/W Bit Val Remarks SINGLE_TURN_RES (Default: 0x00) 4:0 9:5 RW 11:10 Number of angle data bits within one revolution = SINGLE_TURN_RES + 1. Set SINGLE_TURN_RES < 31. U MULTI_TURN_RES (Default: 0x00) Number of data bits for revolution count = MULTI_TURN_RES + 1 U STATUS_BIT_CNT (Default: 0x0) U Number of status data bits 15:12 Reserved.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 195/230 Motor Driver Settings Register STEP_CONF 0x0A STEP_CONF 0x0A (Default: 0x00FB0C80) R/W Bit Val Remarks MSTEP_PER_FS (Default: 0x0) 3:0 RW 15:4 0 Highest microsteps resolution: 256 microsteps per fullstep. i Set to 256 for closed-loop operation. i When using a Step/Dir driver, it must be capable of a 256 resolution via Step/Dir input for best performance (but lower resolution Step/Dir drivers can be used as well).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 196/230 Event Selection Registers 0x0B..0X0D Event Selection Registers R/W Addr Bit Remarks SPI_STATUS_SELECTION (Default: 0x82029805) 0x0B Events selection for SPI datagrams: Event bits of EVENTS register 0x0E that are selected (=1) in this register are 31:0 forwarded to the eight status bits that are transferred with every SPI datagram (first eight bits from LSB are significant!).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 197/230 Status Event Register (0x0E) Status Event Register EVENTS 0x0E R/W Bit Description 0 TARGET_REACHED has been triggered. 1 POS_COMP_REACHED has been triggered. 2 VEL_REACHED has been triggered. 3 VEL_STATE = b’00 has been triggered (VACTUAL = 0). 4 VEL_STATE = b’01 has been triggered (VACTUAL > 0). 5 VEL_STATE = b’10 has been triggered (VACTUAL < 0). 6 RAMP_STATE = b’00 has been triggered (AACTUAL = 0, VACTUAL is constant).
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 199/230 Various Configuration Registers: S/D, Synchronization, etc. Various Configuration Registers: Closed-loop, Switches… R/W Addr Bit 15:0 0x10 31:16 Val Description STP_LENGTH_ADD (Default: 0x0000) U Additional length [# clock cycles] for active step polarity of a step at STPOUT. DIR_SETUP_TIME (Default: 0x0000) U Delay [# clock cycles] between DIROUT and STPOUT voltage level changes.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 200/230 PWM Configuration Registers PWM Configuration Registers R/W Addr Bit Val Description PWM_VMAX (Default:0x00000000) 0x17 23:0 U (Voltage PWM is enabled) PWM velocity value at which maximal scale parameter value 1.0 is reached. 2nd assignment: Also used as VDRV_SCALE_LIMIT if Voltage PWM is disabled (19.29. ) RW 0x1F 15:0 PWM_FREQ (Default: 0x0280) U (Voltage PWM is enabled) Number of clock cycles for one PWM period.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 201/230 Ramp Generator Registers Ramp Generator Registers R/W Addr Bit Val Description RAMPMODE (Default:0x0) Operation Mode: 2 1 Positioning mode: XTARGET is superior target of velocity ramp. 0 Velocitiy mode: VMAX is superior target of velocity ramp. RW Motion Profile: 0x20 0 1:0 1 2 RW 0x21 31:0 R 0x22 31:0 R 0x23 31:0 No ramp: VACTUAL follows only VMAX (rectangle velocity shape). Trapezoidal ramp (incl.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 202/230 Ramp Generator Registers R/W Addr Bit Val Description VSTOP (Default:0x00000000) 0x26 30:0 U Absolute stop velocity in positioning mode and velocity mode. In case VSTOP is used: no last bow phase B4 for S-shaped ramps. In case VSTOP is very small and positioning mode is used, it is possible that the ramp is finished with a constant VACTUAL = VSTOP until XTARGET is reached.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 203/230 Ramp Generator Registers R/W Addr Bit Val Description ASTART (Default: 0x000000) S-shaped ramp motion profile: start acceleration value. Trapezoidal ramp motion profile: Acceleration value in case |VACTUAL| < VBREAK. 0x2A 23:0 Acceleration value after switching from external to internal step control.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 204/230 Ramp Generator Registers R/W Addr Bit Val Description BOW1 (Default: 0x000000) Bow value 1 (first bow B1 of the acceleration ramp). 0x2D 23:0 U Value representation: Frequency mode: [pulses per sec3] 24 digits and 0 decimal places: 1 pps3 ≤ BOW1 ≤ 16 Mpps3 Direct mode: [∆a per clk cycle] bow[av per clk_cycle]= BOW1 / 253 BOW1 [pps3] = BOW1 / 253 • fCLK3 Consider maximum values, represented in section 6.7.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 205/230 External Clock Frequency Register External Clock Frequency Register R/W Addr Bit RW 0x31 24:0 Val Description CLK_FREQ (Default: 0x0F42400) U External clock frequency value fCLK [Hz] with 4.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 206/230 Pipeline Registers Pipeline Register R/W Addr Bit Val 0x38 31:0 S X_PIPE0 (Default: 0x00000000): 1st pipeline register. 0x39 31:0 S X_PIPE1 (Default: 0x00000000): 2nd pipeline register. 0x3A 31:0 S X_PIPE2 (Default: 0x00000000): 3rd pipeline register. 0x3B 31:0 S X_PIPE3 (Default: 0x00000000): 4th pipeline register. 0x3C 31:0 S X_PIPE4 (Default: 0x00000000): 5th pipeline register.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 207/230 Freeze Register The freeze register can only be written once after an active reset and before motion starts. It is always readable. FREEZE Register R/W Addr Bit Val Description DFREEZE (Default: 0x000000) 23:0 RW Freeze event deceleration value. In case NFREEZE switches to low level, this parameter is used for an automatic linear ramp stop. Setting DFREEZE to 0 leads to an hard stop.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 208/230 Encoder Registers Encoder Registers R/W Addr Bit Val Description RW 0x50 31:0 S Actual encoder position [µsteps]. ENC_LATCH (Default: 0x00000000) R S 0x51 31:0 W Latched encoder position. ENC_RESET_VAL(Default: 0x00000000) S Defined reset value for ENC_POS in case the encoder position must be cleared to another value than 0.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 209/230 Encoder Registers R/W Addr Bit Val Description 15:0 0x56 31:16 SER_CLK_IN_HIGH (Default: 0x00A0) U High voltage level time of serial clock output [# clock cycles]. SER_CLK_IN_LOW (Default: 0x00A0) U Low voltage level time of serial clock output [# clock cycles]. SSI_IN_CLK_DELAY (Default: 0x0000) 15:0 U SSI encoder: Delay time [# clock cycles] between next data transfer after a rising edge of serial clock output.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 210/230 PID & Closed-Loop Registers PID and Closed-Loop Registers R/W Addr Bit Val Description CL_BETA (0x0FF) 8:0 U RW 0x1C Maximum commutation angle for closed-loop regulation. i i Set CL_BETA > 255 carefully (esp. if cl_vlimit_en = 1). Exactly 255 is recommended for best performance. CL_GAMMA (Default:0xFF) 23:16 U Maximum balancing angle to compensate back-EMF at higher velocities during closed-loop regulation.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 W 19:0 0x5F W 211/230 PID_TOLERANCE (Default:0x00000) U (PID regulation) Tolerated position deviation: PID_E = 0 in case |PID_E| < PID_TOLERANCE CL_TOLERANCE (Default:0x00) 7:0 U (Closed-loop operation) Tolerated position deviation: CL_DELTA_P = 65536 (gain=1) in case |ENC_POS_DEV| < CL_TOLERANCE CL_VMIN_EMF (Default:0x000000) W 0x60 23:0 U (Closed-loop operation) Encoder velocity at which back-EMF compensation starts.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 212/230 dcStep Registers Micellaneous Registers R/W Addr Bit Val Description DC_VEL (Default:0x000000) 0x60 23:0 Minimum dcStep velocity [pps]. In case|VACTUAL| > DC_VEL dcStep is active, if enabled. 2nd assignment: Also used as CL_VMIN_EMF if closed-loop is enabled (section 19.26. ) 3rd assignment: Also used as FS_VEL if no dcStep or closed-loop is enabled (see 19.16.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 213/230 Transfer Registers Transfer Registers R/ Addr Bit Val Description W ADDR_TO_ENC (Default:0x00000000) W 0x68 31:0 W 0x69 31:0 - (SPI encoders only) Address data permanently sent to get encoder angle data from the SPI encoder slave device. Address data sent from TMC4361A to SPI encoder for one-time data transfer.
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TMC4361A Datasheet | Document Revision 1.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 215/230 SPI-DAC Configuration Registers SPI-DAC Configuration Registers R/W Addr Bit Val Description DAC_ADDR_A (Default:0x0000) 15:0 U Fixed command/address, which is sent via SPI output before sending CURRENTA_SPI values. DAC_ADDR_B (Default: 0x0000) RW 0x1D 31:16 U Fixed command/address, which is sent via SPI output before sending current CURRENTB_SPI values.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 216/230 20. Absolute Maximum Ratings The maximum ratings may not be exceeded under any circumstances. Operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. Maximum Ratings: 3.3V supply Parameter (VCC = 3.3V nominal  TEST_MODE = 0V) Supply voltage Input voltage IO Symbol Min Max Unit VCC VIN 3.0 −0.3 3.6 3.6 V V Symbol Min Max Unit VCC VIN 4.8 −0.3 5.2 5.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 217/230 21. Electrical Characteristics DC characteristics contain the spread of values guaranteed within the specified supply voltage range unless otherwise specified. Typical values represent the average value of all parts measured at +25°C. Temperature variation also causes stray to some values. A device with typical values will not leave Min/Max range within the full temperature range.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 218/230 General IO Timing Parameters General IO Timing Parameters Parameter Symbol Conditions Min Typ Max 30 Operation frequency fCLK fCLK = 1 / tCLK 4.21) 16 Clock Period tCLK Rising edge to rising edge 33.5 62.5 Unit MHz ns Clock time low 16.5 ns Clock time high 16.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Layout Examples Internal Cirucit Diagram for Layout Example Figure 73: Internal Circuit Diagram for Layout Example © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Components Assembly for Application with Encoder Figure 74: Components Assembly for Application with Encoder Top Layer: Assembly Side Figure 75: Top Layer: Assembly Side © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Inner Layer (GND) Figure 76: Inner Layer (GND) Inner Layer (Supply VS) Figure 77: Inner Layer (Supply VS) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 222/230 Package Dimensions Package Dimensions Parameter Ref Min Nom Max Total thickness A 0.8 0.85 0.9 0.03 0.05 5 0.65 0.67 Stand off A1 0 Mold thickness A2 - Lead frame thickness A3 Lead width b Body size X D 6 BSC Body size Y E 6 BSC Lead pitch e 0.5 BSC Exposed die pad size X J 4.52 4.62 4.72 Exposed die pad size Y K 4.52 4.62 4.72 Lead length L 0.35 0.203 REF 0.2 0.25 0.4 Package edge tolerance aaa 0.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 223/230 Package Material Information Please refer to the associated document “TMC43xx Package Material Information, V1.00” for information about available package dimensions and the various tray and reel package options. This document informs you about outside dimensions per tray and/reel and the number of ICs per tray/reel.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 224/230 A P P E ND I C E S 22. Supplemental Directives ESD-DEVICE INSTRUCTIONS This product is an ESD-sensitive CMOS device. It is sensitive to electrostatic discharge.    Provide effective grounding to protect personnel and machines. Ensure work is performed in a nonstatic environment. Use personal ESD control footwear and ESD wrist straps, if necessary. Failure to do so can result in defects, damages and decreased reliability.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 225/230 of patents or other rights of third parties which may result from its use. Specifications are subject to change without notice. Disclaimer: Intended Use The data specified in this user manual is intended solely for the purpose of product description.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 226/230 23. Tables Index Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1: TMC4361A Order Codes ..............................................................................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 227/230 Table 58: Index Channel Sensitivity ...................................................................................................... 146 Table 59: Supported SPI Encoder Data Transfer Modes ......................................................................... 156 Table 60: Dedicated Closed-Loop and PID Registers ..............................................................................
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 228/230 24.
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 229/230 58: TMC4361A connected with TMC23x/24x operating in SPI Mode or PWM Mode ........................ 133 59: dcStep extended Application Operation Area ......................................................................... 136 60: Velocity Profile with Impact through Overload Situation ..
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TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 230/230 25. Revision History Document Revision History Version Date Author Description 1.00 2014-APR-11 HS, SD First complete version. New release variant, which is a product upgrade of TMC4361. New chapter organization with additional information. Specifically for: 1.10 2016-JUL-20 HS, SV   Chapter 17: Reset and Clock Gating, page 169. Chapter 18: Serial Encoder Output, page 172 . New Layout, ANSI-compliant safety notices. 1.