Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 56
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
18 On-Chip Voltage Regulator
The on-chip voltage regulator delivers a 3.3V supply for the chip core. An external 470nF ceramic
capacitor has to be connected between the V33 pin (see Figure 18-1, page 56) and ground, with
connections as short as possible. Additionally, an external 100nF ceramic capacitor (CBLOCK) has to
be connected between pin V5 and ground with connections as short as possible in 5V operational
mode. In 3.3V operational mode an external 100nF ceramic capacitor (see Figure 18-1, page 56) is
necessary only between pin V33 and ground, with connections as short as possible.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TRANGEREG
Temperature range
Industrial
-40
85
°C
VDD5REG
Supply voltage vdd5
5 V Operational Mode
4.5
5
5.5
V
CBLOCK
Block capacitor
5 V Operational Mode, x7r ceramic capacitor
100
nF
VDD3REG
Supply voltage vdd3
3.3 V Operational Mode
2.9
3.3
3.6
V
ICCNLREG
Current consumption
no load
50
100
µA
tSREG
Startup time
no external capacitor connected
20
µs
tSREGC
Startup time
C_load = 470 nF
150
µs
TDRFT
Temperature drift
300
ppm / °C
VRIPPLE
Ripple on vdd3
With ripple over 50 mV the input thresholds
may differ from that specified in the data sheet
100
mV
CREG
External capacitor
On V33 pin, x7r ceramic, necessary capacity
depending on ripple requirements. Using
external capacitor with capacity other than
typical, the ripple should be measured on pin
v33 to be sure that requirements are satisfied.
33
470
nF
COPT
Optional capacitor
Optional parallel capacitor for additional
reduction of high frequency ripple, c0g
ceramic, unnecessary in most cases
470
pF
PSRRDC
power supply ripple
rejection
DC
50
dB
Table 18-1: Characteristics of the on-chip voltage regulator
SCK_S
SDO_S
SDI_S
nSCS_S
REF2 REF3
REF1
TEST GND
SDI_C
nSCS_C
SCK_C
SDO_C
CLK
V5V33
TMC428 / TMC429
470 nF
*
+5 V
100 nF
*
Copt
5V Operation (TTL)
Pinns named GND and TEST have to be connected to
ground as close as possible to the chip.
* Capacitors should be placed as
cloase as possible to the chip.
SCK_S
SDO_S
SDI_S
nSCS_S
REF2 REF3
REF1
TEST GND
SDI_C
nSCS_C
SCK_C
SDO_C
CLK
V5V33
TMC428 / TMC429
+3.3V
100nF
*
3.3V Operation (CMOS)
The optional capacitor Copt is unnecessary in most cases.
Figure 18-1: 3.3V operation (CMOS) vs. 5V operation (TTL)