Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 40
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
10.14 Simultanous Start of up to Three Stepper Motors
Starting stepper motors simultaneously can be acheved by sending successive datagrams starting the
stepper motors. If the delay between those datagrams is of the magnitude of some microseconds, the
stepper motors can be considered as started simultaneously. Feeding the reference switch signals
through or gates (see Figure 10-10) allows exact simultaneous start of the stepper motors under
software control.
SCK_S
SDO_S
SDI_S
nSCS_S
REF2 REF3
REF1
TEST GND
SDI_C
nSCS_C
SCK_C
SDO_C
CLK
V5V33
TMC428 / TMC429
A1
A0
A < MUX
B
C
D
B1
B0
C1
C0
D1
D0
SEL1/ /0
/EN
REF1_LEFT REF1_RIGHT
REF2_LEFT
REF2_RIGHT
REF3_LEFT
REF3_RIGHT
+VCC
74HC157
74HC32
hold
SCK_S
SDO_S
SDI_S
nSCS_S
REF2R REF3
REF1R
TEST GNDCLK
V5V33
TMC429-LI
SCK_C
SDI_C
nSCS_C
SDOZ_C
nINT_SDO_C
REF1
REF3RREF2
hold
Figure 10-10: Reference switch gateing for exact simultanous stepper motor start
11 RAM Address Partitioning and Data Organization
The on-chip RAM capacity is 128 x 6 bit. These 128 on-chip RAM cells of 6 bit width are addressed via
64 addresses of 2 x 6 bit (see Table 11-1). So, from the point of view of addressing the on-chip RAM
via datagrams, the address space enfolds 64 addresses of 24 bit wide data, where only 2 x 6 = 12 bits
are relevant. These 64 addresses are partitioned selected by the RRS (Register RAM Select,
datagram bit 31) into two address ranges of 32 addresses. The registers of the TMC429 are
    -        -chip RAM
addresses are partitioned into two separate ranges by the most significant address bit of the datagram
(bit 30).
The first 32 addresses are provided for the configuration of the serial stepper motor driver chain. Each
of these 32 addresses stores two configuration words, composed of the so called NxM (Next Motor) bit
together with the 5 bit wide primary signal code. While sending a datagram, the primary signal code
words are read internally beginning with the first address of the driver chain datagram configuration
memory range. Each primary signal code word selects a signal provided by the micro step unit. If the
    ing counter is incremented. If this internal counter is
equivalent to the LSMD (last stepper motor driver) parameter, the datagram transmission is finished
and the counter is preset to %00 for the next datagram transmission to the stepper motor driver chain.
The second 32 addresses are provided to store the micro step table, which usually is a quarter sine
wave period as a basic approach or the quarter period of a periodic function optimized for
microstepping of a given stepper motor type. Different stepper motors may step with different micro
step resolutions, but the micro step look up table (LUT) is the same for all stepper motors controlled by
one TMC429. Any quarter wave period stored in the micro step table is expanded automatically to a full
period wave together with its 90° phase shifted wave.