Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 34

10.5.1 TMC429 Step/Direction Timning

The step direction mode is enabled while the "ENable StepDirection" control bit EN_SD of the

if_configuration_429 register is set to '1'. The timing of the step direction interface is controllen by the

four LSBs  of the clk2_div of the global parameter register.    

stpdiv_429. For a given clock frequency fCLK[in unit MHz] of the TMC429, the length tSTEP [in unit

µs] of a step pulse is

tSTEP[µs] = 16 * ( 1 + stpdiv_429 ) / fCLK[MHz].

So, for a clock frequency fCLK[MHz] of 16MHz the step pulse length can be programmed by

stpdiv_429 in integrer multiple of 1 µs. The stpdiv_429 must be set that it is compatible to the upper

step frequency fSTEP = 1 / tSTEP that is used. The first step pulse after a change of direction is

delayed by tDIR2STP that is equal to tSTEP to avoid setup time violations of the step direction power

stage.

General, the maximum step pulse frequency fSTEP_MAX[MHz] = fCLK[MHz] / 32. For a clock

frequency fCLK[MHz] = 16MHz the maximal possible step pulse frequency fSTEP_MAX is 500kHz. For

a clock frequency fCLK[MHz] = 32MHz the maximal step pulse frequency fSTEP_MAX is 1MHz.

STP

DIR

tSTEP

tDIR2STP = tSTEP

tSTEP

tDIR2STP = tSTEP

Figure 10-3: TMC429 Step Direction Timing (EN_SD='1' & STEP_HALF='0')

10.6 pos_comp_429 (JDX=%0101)

Position compare register of the TMC429 that gives a pulse on POSCMP output if the actual position

x_actual of the motor selected by pos_comp_sel is equal to the compate position stored in register

pos_comp_429.

10.7 pos_comp_int_429 (JDX=%0110)

The position compare interrupt mask (M) and interrupt flag (I) register hold the mask and interrupt

concerning the pos_comp function of the TMC429. In principle, these bits could have been added to

the existing interrupt mask and interrupt flags in the interrupt register address of the TMC428 but these

TMC429 specific interrupt bits are in placed in separate register address.

10.8 power_down (JDX=%1000)

A write to the register address named power_down sets the TMC429 into the power down mode until

it detects a falling edge at the pin nSCS_C. During power down, all internal clocks are stopped, all

outputs remain stable, and all register contents are preserved.

10.9 type_and_version_429 (JDX=%1001)

Read only register that gives type und version of the design. For the TMC428, a read access on this