Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 27
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
Note: Definition of the reference switch by the configuration bit REF_RnL has no effect on the stop
function of the reference switches if DISABLE_STOP_L=’0’ respectively DISABLE_STOP_R=’0’. The
bit REF_RnL 
the right, else 
The bits contained in ref_conf control the semantic and the actions of the reference/stop switch
modes for interrupt generation as explained later. The stepper motor stops if the reference/stop switch,
which corresponds to the actual driving direction, becomes active. The configuration bits named
DISABLE_STOP_L respectively DISABLE_STOP_R disable these automatic stop functions. If the bit
SOFT_STOP is set, motor stop forced by a reference switch is done within motion parameter limits
while otherwise stopping is abruptly.
Hint: There is a functional difference between reference switches and stop switches. Reference
switches are used to determine a reference position for a stepper motor. Stop switches are used for
automatic stopping a motor when reaching a limit. The signals of switches are processed via the inputs
named REF1, REF2, REF3 might be used as automatic stop switches, reference switches, or both.
32 bit DATAGRAM sent from a µC to the TMC429
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
RRS
ADDRESS
RW
DATA
0
smda
1
0
1
0
lp
ref_conf
rm
latched position (waiting)
REF_RnL
SOFT_STOP
DISABLE_STOP_R
DISABLE_STOP_L
%00 : RAMP, %01 : SOFT,
%10 : VELOCITY, %11 : HOLD
Table 9-5: lp & ref_conf & ramp_mode (rm) data bit positions
9.13 interrupt_mask & interrupt_flags (IDX=%1011)
The TMC429 provides one interrupt register of eight flags for each stepper motor. Interrupt bits are
named INT_<mnemonic>
              d
MASK_<mnemonic>              
Table 9-7 on
page 28. The interrupt out SDO_C / nINT is set active low  where the interrupt status bit INT is set
active high  when at least one interrupt flag of one motor becomes set. The interrupt mask enables or
disables each interrupt mask individually. So, if the interrupt status is inactive, nINT 