Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 15
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
MSB
32 bit DATAGRAM sent from µC to the TMC429 via pin SDI_C
LSB
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
RRS
ADDRESS
RW
DATA
Table 7-3 : 32 bit DATAGRAM structure sent from µC (MSB sent first)
The 32 bit wide datagrams sent to the TMC429 are assorted in four groups of bits: RRS (register RAM
select) selecting either registers or on-chip RAM; ADDRESS bits addressing memory within the
register set or within the RAM area; RW (read / not write (RW=1 : read / RW=0 : write)) bit
distinguishing between read access and write access; DATA bits for write access for read access
these bits are don’t care       rent internal registers of the TMC429 have
different lengths. So, for some registers only a subset of these 24 data bits is used. Unused data bits

into the 24 data bit space.
The 32 bit wide datagrams received by the µC from the TMC429 contain two groups of bits: STATUS
BITS and DATA BITS. The status bits, sent back with each datagram, carry the most important
information about internal states of the TMC429 and the settings of the reference switches. These
datagrams have the form:
MSB
32 bit DATAGRAM sent back from the TMC429 to µC via pin SDO_C
LSB
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
STATUS BITS
DATA BITS
INT
CDGW
SM3
SM2
SM1
RS3
xEQt3
RS2
xEQt2
RS1
xEQt1
Table 7-4: 32 bit DATAGRAM structure received by µC (MSB received first)
The status bit INT is the internal high active interrupt controller status output signal. Handling of
interrupt conditions without using interrupt techniques is possible by polling this status bit. The interrupt
signal is also directly available at the SDO_C pin of the TMC429 if nSCS_C is high. The pin SDO_C
may directly be connected to an interrupt input of the microcontroller. Since the SDO_C / nINT output
is multiplexed, the microcontroller has to disable its interrupt input while it sends a datagram to the
TMC429, because the SDO_C signal driven by the TMC429 alternates during datagram
transmission. For initialization purposes, the TMC429 enables direct communication between the
microcontroller and the stepper motor driver chain by sending a so called cover datagram (see
sections 10.2 and 10.3). The position cover_position and actual length cover_len of a cover
datagram is specified by writing them into a common register. Writing an up to 24 bit wide cover
datagram to the register cover_datagram will fade in that cover datagram into the next datagram sent
to the stepper motor driver chain. As a default setting, the TMC429 only sends datagrams on demand.
Optionally, continuous update periodic sending of datagrams to the stepper motor driver chain is
also possible. So, the status bit named CDGW (cover datagram waiting) is a handshake signal for the