Datasheet

TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 14
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
Symbol
Parameter
Min
Typ
Max
Unit
tSUCSC
Setup Clocks for nSCS_C
3

CLK periods
tHDCSC
Hold Clocks for nSCS_C
3

CLK periods
tSCKCL
Serial Clock Low
3

CLK periods
tSCKCH
Serial Clock High
3

CLK periods
tSD
SDO_C valid after SCK_C low
2.5
3.5
CLK periods
tIS
nINTERRUPT status valid after nSCS_C low
2.5
CLK periods
tSI
SDO_C valid after nSCS_C high
4.5
CLK periods
tDAMAGRAMuC
Datagram Length
3+3 + 32*6 = 198

CLK periods
tDAMAGRAMuC
Datagram Length
12.375

µs
fCLK
Clock Frequency
0
32
MHz
tCLK
Clock Period tCLK = 1 / fCLK
31.25

ns
tPD
CLK-rising-edge-to-Output Propagation Delay
5
ns
Table 7-1: Timing characteristics of the serial microcontroller interface
Symbol
Parameter
Min
Typ
Max
Unit
tSUSCSdrv
8
16
256
CLK periods
tHDSCSdrv
8
16
256
CLK periods
tCKSL
8
16
256
CLK periods
tCKSH
8
16
256
CLK periods
tDAMAGRAMdrv
Datagram Length
8+8+1*16+8+8=48
512+64*512+512= 33792
CLK periods
tDAMAGRAMdrv
Datagram Length @ fCLK = 16
MHz
3
2112
µs
tDAMAGRAMdrv
Datagram Length @ fCLK = 32
MHz
3
1056
µs
tPD
CLK-rising-edge to Outputs Delay
5
ns
Table 7-2: Timing characteristics of the serial stepper motor driver interface
The timing of the serial driver interface is programmable in a wide range. The clock divider provides 16
up to 512 clock cycles (tCLK) for a serial driver interface data clock period. The default duration of a
clock period (tSCKCL+tSCKCH) of the signal nSCS_S is 16+16=32 clock periods of the clock signal
CLK. The minimal duration of a serial interface clock period (tSCKCL+tSCKCH) is 8+8=16 clock cycles
of signal CLK as outlined in Figure 7-3. Also, the polarities of the signals nSCS_S and SCK_S are
programmable to use driver chips from other vendors with inverted polarities without additional glue
logic. The input SDI_S of the serial driver interface must always be driven to a defined level. So, to
                 -up
resistor or a pull-down resistor of 10 K is required at that input.
7.4 Datagram Structure
The microcontroller (µC) communicates with the TMC429 via the four wire (nSCS_C, SCK_C, SDI_C,
SDO_C) serial interface. Each datagram sent to the TMC429 via the pin SDI_C and each datagram
received from the TMC429 via the pin SDO_C is 32 bits long. The first bit sent is the MSB (most
significant bit named sdi_c_bit#31 at Figure 7-1). The last bit sent is the LSB (least significant bit
named sdi_c_bit#0 in Figure 7-1). During reception of a datagram, the TMC429 immediately sends
back a datagram of the same length to the microcontroller. This datagram is the result of the request
from the microcontroller.
With each 32 bit wide datagram the microcontroller sends to the TMC429, it simultaneously receives a
32 bit wide datagram. A read request is distinguished from a write request by one datagram bit named
RW. The TMC429 immediately sends back requested read data in the lower 24 datagram bits. Status
bits are sent back in the higher 8 datagram bits. Datagrams sent from the microcontroller to the
TMC429 have the form: