Datasheet
TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 13
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
The signal nSCS_C has to be high for at least three clock cycles before starting a datagram
transmission. To initiate a transmission, the signal nSCS_C has to be set to low. Three clock cycles
later the serial data clock may go low. The most significant bit (MSB) of a 32 bit wide datagram comes
first and the least significant bit (LSB) is transmitted as the last one. A data transmission is finished by
setting nSCS_C high three or more CLK cycles after the last rising SCK_C slope. So, nSCS_C and
SCK_C change in opposite order from low to high at the end of a data transmission as these signals
change from high to low at the beginning. The timing of the serial microcontroller interface is outlined in
Figure 7-1.
7.3 Serial Peripheral Interface to Stepper Motor Driver Chain
The timing of the serial stepper motor interface is similar to that of the microcontroller interface. It
directly connects to SPI
TM
smart power stepper motor drivers. The SPI
TM
datagram is configurable
individually for each stepper motor driver chip of the daisy chain. It is simply configurable by sending a
fixed sequence of datagrams to the TMC429 to initialize it after power-up. Once initialized, the TMC429
autonomously generates the datagrams for the stepper motor driver daisy chain without any additional
interventions of the microcontroller.
The SPI
TM
datagram for each stepper motor driver is composed of so called primary signal bits
provided by the micro step unit of the TMC429 individually for each stepper motor. Each primary signal
bit is represented by a five bit code word called primary signal code. The order of primary signal bits
forming the SPI
TM
datagrams for the stepper motor driver daisy chain is defined by the order of primary
signal code words in the configuration RAM area.
Hint: For clock frequency fCLK = 16MHz an uppder SPI clock frequency of 1MHz is recommended.
For a clock frequency fCLK = 32MHz an uppder SPI clock frequency of 2MHz is recommended. This
avoids possible issues concerning clock phase polarity between micro controller and TMC429.
CLK
tCLK
SCK_S
nSCS_S
SDI_S
SDO_S
sdi_s_bit#0
tPD tPD tPD
1 x sampled SDI_S
tSUSCSdrv tHDSCSdrv
tCKSL tCKSH
sdo_s_bit#0
sdi_s_bit#n-1
sdo_s_bit#n-1
sdo_s_bit#1
sdi_s_bit#1
sdo_s_bit#n
sdi_s_bit#n
m datagram bits
one full stepper motor driver datagram
tDATAGRAMdrv
1 x sampled SDI_S
m x sampled SDI_S
Figure 7-3: Timing diagram of the serial stepper motor driver interface
To switch to the next motor, an additional bit called next motor bit (NxM-Bit) is prefixed to the five bit
wide primary signal code words. So, the total data word width is six bit. Each NxM-Bit effects an
increment of an internal stepper motor address until the processing for all stepper motors within the
daisy chain is completed. A parameter called LSMD (last stepper motor driver) defines the total
number of stepper motors within the daisy chain. So, the codes written into the serial interface
configuration RAM area represent the mapping of control signals provided by the micro step units to
control bits of the drivers. It might be noted here, that configuring the serial driver interface is much
easier as it might seem here. It is explained in detail, illustrated by examples below (see section 12
Stepper Motor Driver Datagram Configuration, page 41).