Datasheet
TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 12
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
serial data clock input SCK_C. The maximum duration of the serial data clock period is unlimited.
While the µC interface of the TMC429 is idle, the SDO_C signal is the (active low) interrupt status nINT
of the integrated interrupt controller of the TMC429. The timing of the multiplexed interrupt status
signal nINT is characterized by the parameters tIS an tSI (see Table 7-1, page 14).
Hint: If the microcontroller and the TMC429 work on different clock domains that run asynchronous to
each other, the timing of the SPI interface of the microcontroller should be made conservative in the
way that the length of one SPI clock cycle equals 8 or more clock cycles of the TMC429 clock CLK.
This make the system robust concerning frequency drift, jitter, etc.
tSD
tSD
CLK
sdi_c_bit#31
tSCKCL tSCKCHtSUCSC tHDCSC
1 x SDI_C sampled
one full 32 bit datagram
nINTSDO_C
SDI_C
SCK_C
nSCS_C
sdi_c_bit#30 . . . sdi_c_bit#1
30 x sampled SDI_C
sdi_c_bit#0
1 x SDI_C sampled
tCLK
tDATAGRAMuC
sdo_c_bit#31
sdo_c_bit#30 ... sdo_c_bit#1
sdo_c_bit#0
tPD
nINT
tIS
tSD
tSI
tHDCSC tSUCSC
Figure 7-1: Timing diagram of the serial µC interface
A complete serial datagram frame has a fixed length of 32 bit. While the data transmission from the
microcontroller to the TMC429 is idle, the low active serial chip select input nSCS_C and also the serial
data clock signal SCK_C are set to high. While the signal nSCS_C is high, the TMC429 assigns the
status of the internal low active interrupt signal named nINT to the serial data output SDO_C (see
Figure 7-1). The serial data input SDI_C of the TMC429 has to be driven by the microcontroller.
Important Hint: In contrast to most other SPI
TM
compatible devices, the SDO_C signal of the TMC429
connected to the microcontroller, it can simply be realized using a single gate 74HCT1G125. An
additional pin named SDOZ_C is available for the TMC429 with an integrated high impedance driver.
SCK_S
SDO_S
SDI_S
nSCS_S
REF2 REF3
REF1
TEST GNDCLK
V5V33
TMC429
SCK_C
SDI_C
nSCS_C
SDOZ_C
SCK_C
SDI_C
nSCS_C
SDOZ_C
nINT_SDO_C can be configured as non-mulitplexed interrupt output
nINT_SDO_C
nINTSCK_S
SDO_S
SDI_S
nSCS_S
REF2 REF3
REF1
TEST GNDCLK
V5V33
TMC428
SCK_C
SDI_C
nSCS_C
SDO_C
74HCT1G125
SCK_C
SDI_C
nSCS_C
SDOZ_C
nINT
optional multiplexed interrupt output / Hint: disable µC Interrupt
input during SPI access while nSCS_C is low
Figure 7-2 : TMC428 SDO_C output high impedance with single gate 74HCT1G125 vs. The
TMC429 has a dedicated high impedance pin SDOZ_C available and the nINT_SDO_C can be nINT.