Datasheet
TMC429 DATASHEET (v. 1.07 / 2012-AUG-01) 11
Copyright © 2010-2012, TRINAMIC Motion Control GmbH & Co. KG
nSCS_C
SCK_C
SDI_C
SDO_C
serial µC interface
CLK
TEST
multiple
ported RAM
interrupt
controller
serial driver interface
step/direction interface
nSCS_S_S2
SCK_S_D1
SDO_S_S1
SDI_S_D2
[nSCS3_D3]
[nSCS2_S3]
10K
micro step unit
( including
sequencer )
ramp generator
&
pulse generator
REF1
REF2
REF3
voltage
regulator
V5
GND
V33
470nF
power-on
reset
[REF1R]
[REF2R]
[REF3R]
[POSCMP]
[SDOZ_C]
GNDGND
Figure 6-2: TMC429 functional block diagram
7 Serial Peripheral Interfaces
The four pins named SCS_C, SCK_C, SDI_C, and SDO_C form the serial microcontroller interface of
the TMC429. The communication between the microcontroller and the TMC429 takes place via 32 bit
datagrams of fixed length. Concerning communication, the µC is the master and the TMC429 is the
slave, with the TMC429 in turn being the master for the stepper motor driver daisy chain. Similar to the
microcontroller interface, the TMC429 uses a four wire serial interface for communication with the
stepper motor driver daisy chain. The four pins named SCS_S, SCK_S, SDO_S, SDI_S form the serial
stepper motor driver interface. Stepper motor drivers with parallel inputs can be used in connection
with the TMC429 with some additional glue logic.
7.1 Automatic Power-On Reset
The TMC429 performs an automatic power-on reset. For details see section Power-On-Reset, page
57. The TMC429 cannot be accessed before the power-on-reset is completed and the clock is stable.
All -divider clk2_div
(see section 10.11, page 35) that is initialized with 15.
7.2 Serial Peripheral Interface for µC
The serial microcontroller interface of the TMC429 behaves as a simple 32 bit shift register. It shifts
serial data SDI_C in with the rising edge of the clock signal SCK_C and copies the content of the 32 bit
shift register with the rising edge of the selection signal nSCS_C into a buffer register. The serial
interface of the TMC429 immediately sends back data read from registers or read from internal RAM
via the signal SDO_C. The signal SDO_C can be sampled with the rising edge of SCK_C, but SDO_C
becomes valid at least four CLK clock cycles after SCK_C becomes low as outlined in the timing
diagram Figure 7-1. For detailed timing parameters see Table 7-1, page 14. The SPI signals from the
µC interface may be asynchronous to the clock signal CLK of the TMC429.
Because of on-the-fly processing of the input data stream, the serial microcontroller interface of the
TMC429 requires the serial data clock signal SCK_C to have a minimum low / high time of three clock
cycles. The data signal SDI_C driven by the microcontroller has to be valid at the rising edge of the