Datasheet

TMC2660 DATASHEET (Rev. 1.05 / 2016-JUL-14) 7
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Pin
Number
Type
Function
SDI
15
DI VIO
SPI serial data input.
(Scan test input in test mode.)
SCK
16
DI VIO
Serial clock input of SPI interface.
(Scan test shift enable input in test mode.)
GND
17, 39,
44
Digital and analog low power GND.
CSN
18
DI VIO
Chip select input for the SPI interface. (Active low.)
ENN
19
DI VIO
Power MOSFET enable input. All MOSFETs are switched off when
disabled. (Active low.)
CLK
21
DI VIO
System clock input for all internal operations. Tie low to use the
on-chip oscillator. A high signal disables the on-chip oscillator until
power down.
VHS
35
High-side supply voltage (motor supply voltage - 10V)
VS
36
Motor supply voltage
TST_ANA
37
AO VIO
Reserved. Do not connect.
SG_TST
38
DO VIO
stallGuard2 output. Signals a motor stall. (Active high.)
VCC_IO
40
Input/output supply voltage VIO for all digital pins. Tie to digital
logic supply voltage. Operation is allowed in 3.3V and 5V systems.
DIR
41
DI VIO
Direction input. Sampled on an active edge of the STEP input to
determine stepping direction. Sampling a low increases the
microstep counter, while sampling a high decreases the counter. A
60-ns internal glitch filter rejects short pulses on this input.
STEP
42
DI VIO
Step input. Active edges can be rising or both rising and falling, as
controlled by the DEDGE mode bit. A 60-ns internal glitch filter
rejects short pulses on this input.
TST_MODE
43
DI VIO
Test mode input. Puts IC into test mode. Tie to GND for normal
operation.
n.c.
1, 33
No internal connection - can be tied to any net, e.g., in order to
improve power routing to pins VSA and VSB.