Datasheet

TMC2660 DATASHEET (Rev. 1.05 / 2016-JUL-14) 18
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6.4.2 Read Response Overview
The table below shows the formats for the read response. The RDSEL parameter in the DRVCONF
register selects the format of the read response.
Bit
RDSEL=%00
RDSEL=%01
RDSEL=%10
19
MSTEP9
SG9
SG9
18
MSTEP8
SG8
SG8
17
MSTEP7
SG7
SG7
16
MSTEP6
SG6
SG6
15
MSTEP5
SG5
SG5
14
MSTEP4
SG4
SE4
13
MSTEP3
SG3
SE3
12
MSTEP2
SG2
SE2
11
MSTEP1
SG1
SE1
10
MSTEP0
SG0
SE0
9
-
-
-
8
-
-
-
7
STST
6
OLB
5
OLA
4
S2GB
3
S2GA
2
OTPW
1
OT
0
SG
6.5 Driver Control Register (DRVCTRL)
The format of the DRVCTRL register depends on the state of the SDOFF mode bit.
SPI Mode SDOFF bit is set, the STEP/DIR interface is disabled, and DRVCTRL is the interface for
specifying the currents through each coil.
STEP/DIR Mode SDOFF bit is clear, the STEP/DIR interface is enabled, and DRVCTRL is a configuration
register for the STEP/DIR interface.
6.5.1 DRVCTRL Register in SPI Mode
DRVCTRL
Driver Control in SPI Mode (SDOFF=1)
Bit
Name
Function
Comment
19
0
Register address bit
18
0
Register address bit
17
PHA
Polarity A
Sign of current flow through coil A:
0: Current flows from OA1 pins to OA2 pins.
1: Current flows from OA2 pins to OA1 pins.
16
CA7
Current A MSB
Magnitude of current flow through coil A. The range is
0 to 248, if hysteresis or offset are used up to their full
extent. The resulting value after applying hysteresis or
offset must not exceed 255.
15
CA6
14
CA5
13
CA4
12
CA3
11
CA2
10
CA1
9
CA0
Current A LSB