Datasheet

TMC2660 DATASHEET (Rev. 1.05 / 2016-JUL-14) 17
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Figure 6.2 shows the interfaces in a typical application. The SPI bus is used by an embedded MCU to
initialize the control registers of both a motion controller and one or more motor drivers. STEP/DIR
interfaces are used between the motion controller and the motor drivers.
6.4 Register Write Commands
An SPI bus transaction to the TMC2660 is a write command to one of the five write-only registers that
hold configuration parameters and mode bits:
Register
Description
Driver Control Register
(DRVCTRL)
The DRVCTRL register has different formats for controlling the
interface to the motion controller depending on whether or
not the STEP/DIR interface is enabled.
Chopper Configuration Register
(CHOPCONF)
The CHOPCONF register holds chopper parameters and mode
bits.
coolStep Configuration Register
(SMARTEN)
The SMARTEN register holds coolStep parameters and a mode
bit. (smartEnergy is an earlier name for coolStep.)
stallGuard2 Configuration Register
(SGCSCONF)
The SGCSCONF register holds stallGuard2 parameters and a
mode bit.
Driver Configuration Register
(DRVCONF)
The DRVCONF register holds parameters and mode bits used to
control the power MOSFETs and the protection circuitry. It also
holds the SDOFF bit which controls the STEP/DIR interface and
the RDSEL parameter which controls the contents of the
response returned in an SPI transaction
In the following sections, multibit binary values are prefixed with a % sign, for example %0111.
6.4.1 Write Command Overview
The table below shows the formats for the five register write commands. Bits 19, 18, and sometimes
17 select the register being written, as shown in bold. The DRVCTRL register has two formats, as
selected by the SDOFF bit. Bits shown as 0 must always be written as 0, and bits shown as 1 must
always be written with 1. Detailed descriptions of each parameter and mode bit are given in the
following sections.
Register/
Bit
DRVCTRL
(SDOFF=1)
DRVCTRL
(SDOFF=0)
CHOPCONF
SMARTEN
SGCSCONF
DRVCONF
19
0
0
1
1
1
1
18
0
0
0
0
1
1
17
PHA
0
0
1
0
1
16
CA7
0
TBL1
0
SFILT
TST
15
CA6
0
TBL0
SEIMIN
0
SLPH1
14
CA5
0
CHM
SEDN1
SGT6
SLPH0
13
CA4
0
RNDTF
SEDN0
SGT5
SLPL1
12
CA3
0
HDEC1
0
SGT4
SLPL0
11
CA2
0
HDEC0
SEMAX3
SGT3
0
10
CA1
0
HEND3
SEMAX2
SGT2
DISS2G
9
CA0
INTPOL
HEND2
SEMAX1
SGT1
TS2G1
8
PHB
DEDGE
HEND1
SEMAX0
SGT0
TS2G0
7
CB7
0
HEND0
0
0
SDOFF
6
CB6
0
HSTRT2
SEUP1
0
VSENSE
5
CB5
0
HSTRT1
SEUP0
0
RDSEL1
4
CB4
0
HSTRT0
0
CS4
RDSEL0
3
CB3
MRES3
TOFF3
SEMIN3
CS3
0
2
CB2
MRES2
TOFF2
SEMIN2
CS2
0
1
CB1
MRES1
TOFF1
SEMIN1
CS1
0
0
CB0
MRES0
TOFF0
SEMIN0
CS0
0