Datasheet

TMC262 / TMC262C DATASHEET (Rev. 2.22 / 2019-FEB-22) 48
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Time
V
VS
Device in reset: all
registers cleared to 0
V
UV
V
VCC_IO
max. VCC_IO
Device in reset: all
registers cleared to 0
Defined clock, no intermediate levels
allowed
CLK must be low, while VCC_IO is below V
INHI
V
INHI
3.3V/5V
Operation, CLK is not allowed to have undefined
levels between V
INLO
and V
INHI
and timing must
satisfy T
CLK
(min)
V
CLK
Figure 13.1 Start-up requirements of CLK input
13.1 Frequency Selection
A higher frequency allows faster step rates, faster SPI operation, and higher chopper frequencies. On
the other hand, it may cause more electromagnetic emission and more power dissipation in the
digital logic. Generally, a system clock frequency of 10MHz to 16MHz is best for most applications,
unless the motor is to operate at the highest velocities. If the application can tolerate reduced motor
velocity and increased chopper noise, a clock frequency of 4MHz to 10MHz should be considered.
CLK frequency
Comment
internal
13-16MHz, typical.
Tie clock input firmly to GND. See electrical characteristics for limits.
The internal clock is sufficient, unless a good reproducibility of StallGuard
values is desired.
4-10 MHz
Lower range sufficient for higher inductance motors
10-16 MHz
Recommended for best results
16-20 MHz
Option in case a lower frequency is not available
Ensure 40-60% duty cycle
>14 MHz
Attention for TMC262C, date code 1837 only:
Minimum high-level time of 27ns is required for switching to external clock.
Ensure min. 45% duty cycle of CLK signal up to 16Mhz.
> 16MHz not recommended.