Datasheet

TMC262 / TMC262C DATASHEET (Rev. 2.22 / 2019-FEB-22) 46
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Time
V
VS
Device in reset: all
registers cleared to 0
Reset
V
UV
ca. 100µs ca. 100µs
Figure 11.2 Undervoltage reset timing
Note
Be sure to operate the IC significantly above the undervoltage threshold to ensure reliable operation!
Check for SE reading back as zero to detect an undervoltage event.
12 Power Supply Sequencing
The TMC262 generates its own 5V supply for all internal operations. The internal reset of the chip is
derived from the supply voltage regulator in order to ensure a clean start-up of the device after
power up. During start up, the SPI unit is in reset and cannot be addressed. All registers become
cleared.
VCC_IO limits the voltage allowable on the inputs and outputs and is used for driving the outputs,
but input levels thresholds are not depending on the actual level of VCC_IO. VCC_IO may start up
before or after VS. However, with a delayed start-up of VCC_IO, care must be taken for systems using
an external clock signal (see next chapter).
For TMC262C, VCC_IO is monitored, and the IC becomes reset upon undervoltage. This way, the
power-up restriction for VCC_IO with external clock signal is relaxed.