Datasheet

TMC2590 DATASHEET (V1.0 / 2019-FEB-22) 50
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Time
V
VS
Device in reset: all
registers cleared to 0
V
UV
V
VCC_IO
max. VCC_IO
Device in reset: all
registers cleared to 0
Defined clock, no intermediate levels
allowed
CLK must be low, while VCC_IO is below V
INHI
V
INHI
3.3V/5V
Operation, CLK is not allowed to have undefined
levels between V
INLO
and V
INHI
and timing must
satisfy T
CLK
(min)
V
CLK
Figure 14.1 Start-up requirements of CLK input
14.1 System Clock Frequency
A higher frequency allows faster step rates, faster SPI operation, and higher chopper frequencies. On
the other hand, it may cause more electromagnetic emission and more power dissipation in the
digital logic. Generally, a system clock frequency of 10MHz to 16MHz should be sufficient for most
applications, unless the motor is to operate at the highest velocities. If the application can tolerate
reduced motor velocity and increased chopper noise, a clock frequency of 4MHz to 10MHz should be
considered.
Status
Description
Range
Comment
EN_S2VS
Set this bit to enable protection against a failing
external CLK source. If set, the IC switches back
to external clock after 32 to 48 internal clock
cycles. At the same time, this bit controls the
higher side short detector sensitivity
0 / 1
Undervoltage level
0: Stopping clock will
stop the IC.
1: CLK fail safe
protection