Datasheet

TMC2590 DATASHEET (V1.0 / 2019-FEB-22) 31
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8 STEP/DIR Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The MicroPlyer STEP pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping and reduces pulse
bandwidth.
8.1 Timing
Figure 8.1 shows the timing parameters for the STEP and DIR signals, and the table below gives their
specifications. When the DEDGE mode bit in the DRVCTRL register is set, both edges of STEP are
active. If DEDGE is cleared, only rising edges are active. STEP and DIR are sampled and synchronized
to the system clock. An internal analog filter removes glitches on the signals, such as those caused by
long PCB traces. If the signal source is far from the chip, and especially if the signals are carried on
cables, the signals should additionally be filtered or differentially transmitted.
DIR
STEP
t
DSH
t
SH
t
SL
t
DSU
Active edge (DEDGE=0) Active edge (DEDGE=0)
Figure 8.1 STEP/DIR timing
STEP and DIR Interface Timing
AC-Characteristics
clock period is t
CLK
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Step frequency (at maximum
microstep resolution)
f
STEP
DEDGE=0
½ f
CLK
DEDGE=1
¼ f
CLK
Fullstep frequency
f
FS
f
CLK
/512
STEP input low time
t
SL
max(t
FILTSD
,
t
CLK
+20)
ns
STEP input high time
t
SH
max(t
FILTSD
,
t
CLK
+20)
ns
DIR to STEP setup time
t
DSU
20
ns
DIR after STEP hold time
t
DSH
20
ns
STEP and DIR spike filtering
time
t
FILTSD
Rising and falling
edge
12
20
40
ns
STEP and DIR sampling relative
to rising CLK input
t
SDCLKHI
Before rising edge
of CLK
t
FILTSD
ns