Datasheet

TMC2590 DATASHEET (V1.0 / 2019-FEB-22) 27
www.trinamic.com
7.9 Driver Control Register (DRVCONF)
DRVCONF
Driver Configuration
Bit
Name
Function
Comment
19
1
Register address bit
18
1
Register address bit
17
1
Register address bit
16
TST
Reserved TEST mode
Must be cleared for normal operation. When set, the
SG_TST output exposes digital test values, and the
TEST_ANA output exposes analog test values.
15
SLPH1
Slope control, high
side
%000: Minimum slope, lowest driver strength
…
%111: Maximum slope, highest driver strength
See table on next page for details
14
SLPH0
13
SLPL1
Slope control, low
side
12
SLPL0
11
SLP2
Slope control MSB
for high side and
low side
10
DIS_S2G
Short to GND
protection disable
0: Short to GND protection is enabled.
1: Short to GND protection is disabled.
9
TS2G1
Short detection delay
for high-side and
low-side FETs
%00: 3.2µs.
%01: 1.6µs.
%10: 1.2µs.
%11: 0.8µs.
8
TS2G0
7
SDOFF
STEP/DIR interface
disable
0: Enable STEP/DIR operation.
1: Disable STEP/DIR operation. SPI interface is used to
move motor.
6
VSENSE
Sense resistor
voltage-based current
scaling
0: Full-scale sense resistor voltage is 325mV.
1: Full-scale sense resistor voltage is 173mV.
(Full-scale refers to a current setting of 31.)
5
RDSEL1
Select value for read
out (RD bits)
%00
Microstep position read back
4
RDSEL0
%01
StallGuard2 level read back
%10
StallGuard2 and CoolStep current level read
back
%11
All status flags and detectors
3
OTSENS
Overtemperature
sensitivity
0: Shutdown at 150°C
1: Sensitive shutdown at 136°C
2
SHRTSENS
Short to GND
detection sensitivity
0: Low sensitivity
1: High sensitivity – better protection for high side FETs
1
EN_PFD
Enable Passive fast
decay
/ 5V undervoltage
threshold
0: No additional motor dampening.
1: Motor dampening to reduce motor resonance at
medium velocity. In addition, this bit reduces the lower
nominal operation voltage limit from 7V to 4.5V
0
EN_S2VS
Short to VS
protection
/ CLK failsafe enable
0: Short to VS and overload protection disabled
1: Protection enabled. In addition, this bit enables
protection against CLK fail, when using an external clock
source.