Datasheet

TMC2590 DATASHEET (V1.0 / 2019-FEB-22) 22
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7.5 Driver Control Register (DRVCTRL)
The format of the DRVCTRL register depends on the state of the SDOFF mode bit.
SPI Mode SDOFF bit is set, the STEP/DIR interface is disabled, and DRVCTRL is the interface for
specifying the currents through each coil.
STEP/DIR Mode SDOFF bit is clear, the STEP/DIR interface is enabled, and DRVCTRL is a configuration
register for the STEP/DIR interface.
7.5.1 DRVCTRL Register in SPI Mode
DRVCTRL
Driver Control in SPI Mode (SDOFF=1)
Bit
Name
Function
Comment
19
0
Register address bit
18
0
Register address bit
17
PHA
Polarity A
Sign of current flow through coil A:
0: Current flows from OA1 pins to OA2 pins.
1: Current flows from OA2 pins to OA1 pins.
16
CA7
Current A MSB
Magnitude of current flow through coil A. The range is
0 to 248, if hysteresis or offset are used up to their full
extent. The resulting value after applying hysteresis or
offset must not exceed 255.
15
CA6
14
CA5
13
CA4
12
CA3
11
CA2
10
CA1
9
CA0
Current A LSB
8
PHB
Polarity B
Sign of current flow through coil B:
0: Current flows from OB1 pins to OB2 pins.
1: Current flows from OB2 pins to OB1 pins.
7
CB7
Current B MSB
Magnitude of current flow through coil B. The range is
0 to 248, if hysteresis or offset are used up to their full
extent. The resulting value after applying hysteresis or
offset must not exceed 255.
6
CB6
5
CB5
4
CB4
3
CB3
2
CB2
1
CB1
0
CB0
Current B LSB