Datasheet

TMC2590 DATASHEET (V1.0 / 2019-FEB-22) 21
www.trinamic.com
7.4.1 Write Command Overview
The table below shows the formats for the five register write commands. Bits 19, 18, and sometimes
17 select the register being written, as shown in bold. The DRVCTRL register has two formats, as
selected by the SDOFF bit. Bits shown as 0 must always be written as 0, and bits shown as 1 must
always be written with 1. Detailed descriptions of each parameter and mode bit are given in the
following sections.
Register/
Bit
DRVCTRL
(SDOFF=1)
DRVCTRL
(SDOFF=0)
CHOPCONF
SMARTEN
SGCSCONF
DRVCONF
19
0
0
1
1
1
1
18
0
0
0
0
1
1
17
PHA
0
0
1
0
1
16
CA7
0
TBL1
0
SFILT
TST
15
CA6
0
TBL0
SEIMIN
0
SLPH1
14
CA5
0
CHM
SEDN1
SGT6
SLPH0
13
CA4
0
RNDTF
SEDN0
SGT5
SLPL1
12
CA3
0
HDEC1
0
SGT4
SLPL0
11
CA2
0
HDEC0
SEMAX3
SGT3
SLP2
10
CA1
0
HEND3
SEMAX2
SGT2
DIS_S2G
9
CA0
INTPOL
HEND2
SEMAX1
SGT1
TS2G1
8
PHB
DEDGE
HEND1
SEMAX0
SGT0
TS2G0
7
CB7
0
HEND0
0
0
SDOFF
6
CB6
0
HSTRT2
SEUP1
0
VSENSE
5
CB5
0
HSTRT1
SEUP0
0
RDSEL1
4
CB4
0
HSTRT0
0
CS4
RDSEL0
3
CB3
MRES3
TOFF3
SEMIN3
CS3
OTSENS
2
CB2
MRES2
TOFF2
SEMIN2
CS2
SHRTSENS
1
CB1
MRES1
TOFF1
SEMIN1
CS1
EN_PFD
0
CB0
MRES0
TOFF0
SEMIN0
CS0
EN_S2VS
7.4.2 Read Response Overview
The table below shows the formats for the read response. The RDSEL parameter in the DRVCONF
register selects the format of the read response.
Bit
RDSEL=%00
RDSEL=%01
RDSEL=%10
RDSEL=%11
19
MSTEP9
SG9
SG9
UV_7V
18
MSTEP8
SG8
SG8
ENN input
17
MSTEP7
SG7
SG7
S2VSB
16
MSTEP6
SG6
SG6
S2GB
15
MSTEP5
SG5
SG5
S2VSA
14
MSTEP4
SG4
SE4
S2GA
13
MSTEP3
SG3
SE3
OT150
12
MSTEP2
SG2
SE2
OT136
11
MSTEP1
SG1
SE1
OT120
10
MSTEP0
SG0
SE0
OT100
9
0
0
0
1
8
0
0
0
1
7
STST
6
OLB
5
OLA
4
SHORTB
3
SHORTA
2
OTPW
1
OT
0
SG