Datasheet

TMC2300 DATASHEET (Rev. 1.02 / 2019-NOV-06) 50
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12 STEP/DIR Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The microPlyer step pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping.
12.1 Timing
Figure 12.1 shows the timing parameters for the STEP and DIR signals, and the table below gives
their specifications. Only rising edges are active. STEP and DIR are sampled and synchronized to the
system clock. If the signal source is far from the chip, and especially if the signals are carried on
cables, the signals should be filtered or differentially transmitted.
+VCC_IO
SchmittTrigger
0.44 VCC_IO
0.56 VCC_IO
STEP
or DIR
Input
Internal
Signal
DIR
STEP
t
DSH
t
SH
t
SL
t
DSU
Active edge (DEDGE=0) Active edge (DEDGE=0)
Figure 12.1 STEP and DIR timing, Input pin filter
STEP and DIR interface timing
AC-Characteristics
(taking into account possible lowest internal clock generator frequency)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
step frequency (at maximum
microstep resolution)
f
STEP
4
MHz
fullstep frequency
f
FS
8
kHz
STEP input minimum low time
t
SL
120
ns
STEP input minimum high time
t
SH
120
ns
DIR to STEP setup time
t
DSU
20
ns
DIR after STEP hold time
t
DSH
20
ns