Datasheet

TMC2300 DATASHEET (Rev. 1.02 / 2019-NOV-06) 22
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5.1 General Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
Description / bit names
RW
0x00
10
GCONF
Bit
GCONF Global configuration flags
0
set to 0
1
extcap (Reset default=0)
0: Operation without external capacitor on VCP.
1: External capacitor available. No switching delays.
2
set to 0
3
shaft
1: Inverse stepper motor direction
4
diag_index
0: DIAG output normal
1: DIAG pin outputs index pulse flag instead
5
diag_step
0: DIAG output normal
1: DIAG output shows step pulses from internal
pulse generator (toggle upon each step)
6
multistep_filt (Reset default=1)
0: No filtering of STEP pulses
1: Software pulse generator optimization enabled
when fullstep frequency > 750Hz (roughly). TSTEP
shows filtered step time values when active.
7
test_mode
0: Normal operation
1: Enable analog test output on pin DIR
IHOLD[1..0] selects the function of DIR:
0…1: T120, DAC
Attention: Not for user, set to 0 for normal operation!
R+
WC
0x01
3
GSTAT
Bit
GSTAT Global status flags
(Re-Write with ‘1’ bit to clear respective flags)
0
reset
1: Indicates that the IC has been reset since the last
read access to GSTAT. All registers have been
cleared to reset values.
1
drv_err
1: Indicates, that the driver has been shut down
due to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS for
details. The flag can only be cleared when all
error conditions are cleared.
2
u3v5
1: Actual state of the supply voltage comparator. A
high value means that the voltage sinks below
3.5V. This flag is not latched and thus does not
need to be cleared.
R
0x02
8
IFCNT
Interface transmission counter. This register becomes
incremented with each successful UART interface write
access. Read out to check the serial transmission for
lost data. Read accesses do not change the content.
The counter wraps around from 255 to 0.
W
0x03
4
SLAVECONF
Bit
SLAVECONF
11..8
SENDDELAY for read access (time until reply is sent):
0, 1: 8 bit times