Datasheet

TMC220X, TMC222X DATASHEET (Rev. 1.02 / 2017-MAY-16) 57
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11 STEP/DIR Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The microPlyer step pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping.
11.1 Timing
Figure 11.1 shows the timing parameters for the STEP and DIR signals, and the table below gives
their specifications. Only rising edges are active. STEP and DIR are sampled and synchronized to the
system clock. An internal analog filter removes glitches on the signals, such as those caused by long
PCB traces. If the signal source is far from the chip, and especially if the signals are carried on cables,
the signals should be filtered or differentially transmitted.
+VCC_IO
SchmittTrigger
0.44 VCC_IO
0.56 VCC_IO
83k
C
Input filter
R*C = 20ns +-30%
STEP
or DIR
Input
Internal
Signal
DIR
STEP
t
DSH
t
SH
t
SL
t
DSU
Active edge (DEDGE=0) Active edge (DEDGE=0)
Figure 11.1 STEP and DIR timing, Input pin filter
STEP and DIR interface timing
AC-Characteristics
clock period is t
CLK
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
step frequency (at maximum
microstep resolution)
f
STEP
½ f
CLK
fullstep frequency
f
FS
f
CLK
/512
STEP input minimum low time
t
SL
max(t
FILTSD
,
t
CLK
+20)
100
ns
STEP input minimum high time
t
SH
max(t
FILTSD
,
t
CLK
+20)
100
ns
DIR to STEP setup time
t
DSU
20
ns
DIR after STEP hold time
t
DSH
20
ns
STEP and DIR spike filtering time
*)
t
FILTSD
rising and falling
edge
13
20
30
ns
STEP and DIR sampling relative
to rising CLK input
t
SDCLKHI
before rising edge
of CLK input
t
FILTSD
ns
*) These values are valid with full input logic level swing, only. Asymmetric logic levels will increase
filtering delay t
FILTSD
, due to an internal input RC filter.