Datasheet

TMC2160 DATASHEET (Rev. 1.00 / 2018-JUL-30) 12
www.trinamic.com
Pin
TQFP
Type
Function
SRAH
8
AI
Sense resistor for phase A. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRAL and SRAH to eliminate high frequency switching spikes
from other drives or switching of coil B.
SRBH
9
AI
Sense resistor for phase B. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRBL and SRBH to eliminate high frequency switching spikes
from other drives or switching of coil A.
SRBL
10
AI
Sense resistor GND connection for phase B. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.
TST_MODE
11
DI
Test mode input. Tie to GND using short wire.
CLK
12
DI
CLK input. Tie to GND using short wire for internal clock or
supply external clock. Internal clock-fail over circuit protects
against loss of external clock signal.
CSN_CFG3
13
DI
SPI chip select input (negative active) (SPI_MODE=1) or
Configuration input (SPI_MODE=0)
SCK_CFG2
14
DI
SPI serial clock input (SPI_MODE=1) or
Configuration input (SPI_MODE=0)
SDI_CFG1
15
DI
SPI data input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) or
Next address input (NAI) for single wire interface.
SDO_CFG0
16
DIO
SPI data output (tristate) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) or
Next address output (NAO) for single wire interface.
STEP
17
DI
STEP input
DIR
18
DI
DIR input
GNDD
19, 30
Digital GND. Connect to GND plane near pin.
VCC_IO
20, 21
3.3V to 5V IO supply voltage for all digital pins.
SPI_MODE
22
DI
(pd)
Mode selection input. When tied low with SD_MODE=1, the
chip is in standalone mode and pins have their CFG functions.
When tied high, the SPI interface is enabled. Integrated pull
down resistor.
DCEN_
CFG4
23
DI
(pd)
dcStep enable input (SD_MODE=1, SPI_MODE=1) – leave open
or tie to GND for normal operation in this mode (no dcStep).
Configuration input (SPI_MODE=0)
DCIN_
CFG5
24
DI
(pd)
dcStep gating input for axis synchronization (SD_MODE=1,
SPI_MODE=1) or
Configuration input (SPI_MODE=0)
DCO_
CFG6
25
DIO
dcStep ready output (SD_MODE=1).
With SD_MODE=0, pull to GND or VCC_IO
DIAG0
26
DO
(pu+
pd)
Diagnostics output DIAG0.
Interrupt output
Use external pullup resistor with 47k or less in open drain
mode.
DIAG1
27
DO
(pd)
Diagnostics output DIAG1.
Use external pullup resistor with 47k or less in open drain
mode.
DRV_ENN
28
DI
Enable input. The power stage becomes switched off (all
motor outputs floating) when this pin becomes driven to a
high level.