Datasheet
TMC2160 DATASHEET (Rev. 1.03 / 2019-FEB-05) 11
www.trinamic.com
2 Pin Assignments
2.1 Package Outline
25
26
37
24
DRV_ENN
CPO
HA2
BMA1
CA2
VSA
LA1
LA2
VCP
STEP
CB1
HB1
DCIN_CFG5
LB2
HB2
DCEN_CFG4
1
TST_MODE
DIR
VCC_IO
SDO_CFG0
SDI_CFG1
SCK_CFG2
CSN_CFG3
DIAG1
SRAH
GNDA
12VOUT
VCC_IO
CB2
VS
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
36
35
34
33
32
31
30
29
28
27
48
47
46
45
44
43
42
41
40
39
38
BMB1
13
CPI
VCC
5VOUT
PAD = GNDD, GNDP
12
SPI_MODE
BMB2
DCO_CFG6
DIAG0
SRAL
HA1
CA1
TMC2160-TA
TQFP-48
SRBL
SRBH
BMA2
LB1
CLK
GNDD
GNDD
Figure 2.1 TMC2160-TA package and pinning TQFP-EP 48 (7x7mm² body, 9x9mm² with leads)
2.2 Signal Descriptions
Pin
TQFP
Type
Function
HB1
1
High side gate driver output.
CB1
2
Bootstrap capacitor positive connection.
12VOUT
3
Output of internal 11.5V gate voltage regulator and supply pin
of low side gate drivers. Attach 2.2µF to 10µF ceramic
capacitor to GND plane near to pin for best performance. Use
at least 10 times more capacity than for bootstrap capacitors.
In case an external gate voltage supply is available, tie VSA
and 12VOUT to the external supply.
VSA
4
Analog supply voltage for 11.5V and 5V regulator. Normally
tied to VS. Provide a 100nF filtering capacitor.
5VOUT
5
Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic
capacitor to GNDA near to pin for best performance. Output
for VCC supply of the chip.
GNDA
6
Analog GND. Connect to GND plane near pin.
SRAL
7
AI
Sense resistor GND connection for phase A. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.