Datasheet

TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16) 8
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Pin
Number
Type
Function
VCC
33
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). Typically supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
DIE_PAD
-
GND
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
Number
Type
Function
CPO
35
O(VCC)
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
CPI
36
I(VCP)
Charge pump capacitor input: Provide external 22nF or 33nF / 50 V
capacitor to CPO.
VCP
37
Output of charge pump. Provide external 100nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
Number
Type
Function
GND
1
I
unused input, tie to GND
GND
2
I
unused input, tie to GND
CSN/IO0
3
I/O
Chip select input of SPI interface, programmable IO in UART mode
SCK/IO1
4
I/O
Serial clock input of SPI interface, programmable IO in UART mode
SDI/IO2
5
I/O
Data input of SPI interface, programmable IO in UART mode
SDO
8
I/O
Data output of SPI interface (Tristate, enabled with CSN=0), mode
configuration input in UART mode (0 = Normal mode, 1 = Single wire
ring mode – SWIO_P is input, SWIO_N is output)
SWIOP
9
I/O
Single wire I/O (positive). Serial input in ring mode. Multi-purpose
input in SPI mode or encoder 1 N input.
SWION
10
I/O
Single wire I/O (negative) for differential mode. Leave open in non-
differential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
CLK
11
I
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
SWSEL
12
I
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
NEXTADDR
24
I
Address increment (if tied high) for single wire (UART) mode. General
purpose input in SPI mode
DIR2
25
I
Right reference switch input for motor 2, optional DIR input for
STEP/DIR operation of motor 2 or encoder 2 B input
STEP2
26
I
Left reference switch input for motor 2, optional STEP input for
STEP/DIR operation of motor 2
DIR1
27
I
Right reference switch input for motor 1, optional DIR input for
STEP/DIR operation of motor 1 or encoder 2 A input
STEP1
28
I
Left reference switch input for motor 1, optional STEP input for
STEP/DIR operation of motor 1
DRV_ENN
29
I
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
TST_MODE
48
I
Test mode input. Tie to GND using short wire.
-
13, 23, 38
N.C.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)