Datasheet
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16) 22
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Master CPU
(µC with RS485
tranceiver)
TMC2041
#1
NEXTADDR
CSN/IO0
SWIOP
SWION
TMC2041
#2
NEXTADDR
SWIOP
SWION
TMC2041
#3
SWIOP
SWION
A
B
Addressing phase 1: address 0, IO0 high address 1 address 1
Addressing phase 2: program to address 254 & set IO0 low address 0, IO0 high address 1
Addressing phase 3: address 254 program to address 253 & set NAO low address 0, IO0 high
Addressing phase 4: address 254 address 253 program to address 252 & set IO0 low
1k
+V
IO
CSN/IO0
NEXTADDR
EXAMPLE FOR ADDRESSING UP TO 255 TMC2041
Addressing phase X: continue procedure
R
TERM
R
TERM
R
FILT
C
FILT
R
FILT
C
FILT
+V
IO
10k
+V
IO
10k
Figure 5.2 Addressing multiple TMC2041 via differential interface, additional filtering for NEXTADDR
A different scheme (not shown) uses bus switches (like 74HC4066) to connect the bus to the next unit
in the chain without using the NAI input. The bus switch can be controlled in the same fashion, using
the NAO output to enable it (low level shall enable the bus switch). Once the bus switch is enabled it
allows addressing the next bus segment. As bus switches add a certain resistance, the maximum
number of nodes will be reduced.
It is possible to mix different styles of addressing in a system. For example a system using two
boards with each two TMC2041 can have both devices on a board with a different level on NEXTADDR,
while the next board is chained using analog switches separating the bus until the drivers on the first
board have been programmed.