Datasheet

TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16) 17
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4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
SCK
SDI
SDO
t
CC
t
CC
t
CL
t
CH
bit39 bit38 bit0
bit39 bit38 bit0
t
DO
t
ZC
t
DU
t
DH
t
CH
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
AC-Characteristics
clock period: t
CLK
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK valid before or after change
of CSN
t
CC
10
ns
CSN high time
t
CSH
*) Min time is for
synchronous CLK
with SCK high one
t
CH
before CSN high
only
t
CLK
*)
>2t
CLK
+10
ns
SCK low time
t
CL
*) Min time is for
synchronous CLK
only
t
CLK
*)
>t
CLK
+10
ns
SCK high time
t
CH
*) Min time is for
synchronous CLK
only
t
CLK
*)
>t
CLK
+10
ns
SCK frequency using internal
clock
f
SCK
assumes minimum
OSC frequency
4
MHz
SCK frequency using external
16MHz clock
f
SCK
assumes
synchronous CLK
8
MHz
SDI setup time before rising
edge of SCK
t
DU
10
ns
SDI hold time after rising edge
of SCK
t
DH
10
ns
Data out valid time after falling
SCK clock edge
t
DO
no capacitive load
on SDO
t
FILT
+5
ns
SDI, SCK and CSN filter delay
time
t
FILT
rising and falling
edge
12
20
30
ns