Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17

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12 pid_iq_target_limit

13 pid_iq_target_ddt_limit

14 pid_iq_errsum_limit

15 pid_iq_output_limit

16 ipark_cirlim_limit_u_d

17 ipark_cirlim_limit_u_q

18 ipark_cirlim_limit_u_r

19 not_PLL_locked

20 ref_sw_r

21 ref_sw_h

22 ref_sw_l

23 ——-

24 pwm_min

25 pwm_max

26 adc_i_clipped

27 adc_aenc_clipped

28 ENC_N

29 ENC2_N

30 AENC_N

31 reserved

Table 23: Status Flags Register

All controllers have input limiters as oﬀsets can be added to target values and they can be limited to

remain in certain ranges. Also all controller outputs can be limited and the integrating parts (error sum) of

the PI controllers are also limited to controller outputs. If d/dt-limiters are enabled they are also capable of

limiting target values.

If one of these limiters gets active, the ﬂag will go to high state. This is usually a normal operation, when

controllers are working on the borders of their working area. With STATUS_MASK register corresponding

ﬂags can be activated.

Other status ﬂags go to high state whether the voltage limitation is reached (circular limiter in iPark

transformation) or PWM is saturated (pwm_min and pwm_max). This is also usual operation as the current

controller has to deal with voltage limitation at high velocity operation.

The user can also use the status output to generate an IRQ on reference switch or N-channel of encoder.

Also ADC clipping can be monitored which is a good indicator of wrong or faulty behavior.

Remaining wd_error status ﬂag indicates an error on the clock input of the TMC4671 (see following section).

Status ﬂags register can be written directly. It is not possible to clear individual bits.

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