Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17

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4.9.3 PWM Frequency

The PWM counter maximum length register PWM_MAXCNT controls the PWM frequency. For a clock

frequency fCLK = 25 MHz, the PWM frequency fPWM[Hz] = (4.0

fCLK [Hz]) / (PWM_MAXCNT + 1). With fCLK

= 25 MHz and power-on reset (POR) default of PWM_MAXCNT=3999, the PWM frequency fPWM = 25 kHz.

Note

The PWM frequency is the fundamental frequency of the control system. It can be

changed at any time, also during motion for the classic PI controller structure. The

advanced PI controller structure is tied to the PWM frequency and integrator gains

have to be changed. Please make sure to set current measurement decimation

rates to ﬁt PWM period in high performance applications.

4.9.4 PWM Resolution

The base resolution of the PWM is 12 bit internally mapped to 16 bit range. The minimal PWM increment

is 20ns due to the symmetrical PWM with 100 MHz counter frequency. MAX_PWMCNT = 4095 gives the

full resolution of 12 bit with

≈

25 kHz w/ fCLK=25 MHz. MAX_PWMCNT=2047 results in 11 bit resolution,

but with

≈

50kHz w/ fCLK=25 MHz. So the PWM_MAXCNT deﬁnes the PWM frequency, but also aﬀects the

resolution of the PWM.

4.9.5 PWM Modes

The power-on reset (POR) default of the PWM is OFF. The standard PWM scheme is the centered PWM.

Passive braking and freewheeling modes are available on demand. Please refer to section 7 concerning

the settings.

4.9.6 Break-Before-Make (BBM)

One register controls BBM time for the high side, another register controls BBM time for the low side. The

BBM times are programmable in 10 ns steps. The BBM time can be set to zero for gate drivers that have

their own integrated BBM timers.

Figure 39: BBM Timing

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