Datasheet
TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17
34 / 142
4.4.15 Internal Delta Sigma Modulators - Mapping of V_RAW to ADC_RAW
Generally, delta sigma modulators work best for a typical input voltage range of 25% V_MAX . . . 75% V_MAX
(unsigned 0% ... 100%) resp. -75% V_MAX . . . +75% V_MAX (signed -100% ... +100%). For the integrated delta
sigma modulators, this input voltage operation range is recommended with V_MAX = 5V where V_MAX =
3.3V is possible. The table 13 defines the recommended voltage ranges for both 5V and 3.3V analog supply
voltages.
V_SUPPLY[V] (V_MIN[V]) V_MIN25%[V] V_MAX50%[V] V_MAX75%[V] (V_MAX[V])
(3.3) (0.0) (0.825) (1.65) (2.75) (3.3)
5.0 (0.0) 1.250 2.50 3.75 (5.0)
Table 13: Recommended input voltage range from V_MIN25%[V] to V_MAX75%[V] for internal Delta Sigma
Modulators; V_SUPPLY[V] = 5V is recommended for the analog part of the TMC4671.
V_RAW =
V_MAX for V_IN > V_MAX
(V_IN − V_REF) for V_MIN < (V_IN − V_REF) < V_MAX
V_MIN for V_IN < V_MIN
(14)
The resulting raw ADC value is
ADC_RAW = (2
16
− 1) ·
V_RAW
V_MAX
for V_MIN25%[V] < V_RAW < V_MAX75%[V]. (15)
The idealized expression (equation 14) is valid for recommended voltage ranges (table 13) neglecting
deviations in linearities. These deviations primarily depend on different impedance on the analog signal
path, but also on digital parameterization. Finally, the deviation is quantified in terms of resulting ADC
resolution. So, the Delta Sigma ADC engine maps the analog input voltages V_RAW = V_IN - V_REF of voltage
range V_MIN < V_RAW < V_MAX to ADC_RAW values of range
{
0
. . .
(2
16
)
−
1
} <
=
> {0 . . . 65535} <
=
>
0x0000 . . . 0xFFFF.
Vmin[V] Vref[V] Vmax[V] VIN[V] DUTY[%] ADC_RAW
0.0 2.5 5.0 (0.0) (0%) (0x0000)
0.0 2.5 5.0 1.0 25% 0x4000
0.0 2.5 5.0 2.5 50% 0x7fff
0.0 2.5 5.0 3.75 75% 0xC000
0.0 2.5 5.0 (5.0) (100%) (0xffff)
Table 14: Delta Sigma input voltage mapping of internal Delta Sigma Modulators
Info
For calibrating purposes, the input voltage of the delta sigma ADC inputs can be
programmed to fixed voltages (25%, 50%, 75% of analog supply voltage) via the
associated configuration register DS_ANALOG_INPUT_STAGE_CFG.
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