Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17
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4.4.14 Delta Sigma Configuration and Timing Configuration
The delta sigma configuration is programmed via MCFG register that selects the mode (internal/external
delta sigma modulator with programmable MCLK; delta sigma modulator clock mode (MCLK output, MCLK
input, MCLK used as MDAC output with external R-C-R-CMP configuration); delta sigma modulator clock
and its polarity; and the polarity of the delta sigma modulator data signal MDAT).
Info
The power-on delta sigma configuration should fit with most applications when
using the intergated delta sigma ADCs of the TMC4671. Primarily, the default delta
sigma configuration needs to be adapted when using external delta sigma modu-
lators or to select differential ADC input configurations, or in case of enhanced
sampling requirenment for high resolution analog encoders.
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