Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17

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4.4.11 Internal Delta Sigma ADC Input Stage Conﬁguration

ADC channels can be conﬁgured either as diﬀerential ended analog inputs (ADC_I0, ADC_I1, AENC_UX,

AENC_VN, AENC_WY) or as single ended analog inputs (ADC_VM, AGPI_A, AGPI_B). Additionally, the ADC all

channels can be set to ﬁxed voltages (0V, VREF/4, VREF/2, 3*VREF/4) for calibrations purposes.

STAGE_CFG(n+2:n) CONFIGURATION DESCRIPTION COMMENT

0 INP vs. INN diﬀerential mode default conﬁguration

1 GND vs. INN single ended negative INN vs. GND (for test purposes only)

2 VDD/4 25% ADC reference voltage calibration aid

3 3*VDD/4 75% ADC reference voltage calibration aid

4 INP vs. GND single ended mode INP vs. GND (half voltage range, oﬀset)

5 VDD/2 50% ADC reference voltage calibration aid

6 VDD/4 25% ADC reference voltage (redundant conﬁguration)

7 3*VDD/4 75% ADC reference voltage (redundant conﬁguration)

Table 7: Delta Sigma (∆Σ) ADC Input Stage Conﬁgurations

The three bit vector ADC_STAGES_CFG(n+2:n) is part of the DS_ANALOG_INPUT_STAGE_CFG(31:0) with n = 0,

4, 8, 12, 16, 20, 24, 28 for the eigth delta sigma ADC channels. DS_ANALOG_INPUT_STAGE_CFG conﬁgures

the associated delta sigma ADC input stages according to table 15. For association of the bit position (bit

n+2 to bit n) refere register bank section 7.2.

STAGE_CFG(n+2:n) ADC channel function

STAGE_CFG(2:0) ADC_I0 sense voltage of current I0

STAGE_CFG(6:4) ADC_I1 sense voltage of current I1

STAGE_CFG(9:8) ADC_VM down divided supply voltage

STAGE_CFG(10) ’1’ ﬁxed for ADC_VM (STAGE_CFG=4,5,6,7)

STAGE_CFG(13:12) ADC_AGPI_A general purpose analog input A

STAGE_CFG(14) ’1’ ﬁxed for ADC_AGPI_A (STAGE_CFG=4,5,6,7)

STAGE_CFG(17:16) ADC_AGPI_B general purpose analog input B

STAGE_CFG(18) ’1’ ﬁxed for ADC_AGPI_B (STAGE_CFG=4,5,6,7)

STAGE_CFG(22:20) ADC_AENC_UX analog Hall UX / analog encoder COS

STAGE_CFG(26:24) ADC_AENC_VN analog Hall V / analog encoder N

STAGE_CFG(30:28) ADC_AENC_WY analog Hall WY / analog encoder SIN

Table 8: Delta Sigma (∆Σ) ADC Input Stage Conﬁgurations

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