Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17
18 / 142
Info
SPI write access can be performed up to 8 MHz SPI clock frequency. SPI read
access can be performed up to 8 MHz SPI clock frequency if a pause of at least
500 ns is inserted after transfer of the address byte of the SPI datagram. Without
a pause of 500 ns after address byte, SPI read access can be performed up to 2
MHz SPI clock frequency.
Figure 9: SPI Timing of Write Access without pause with fSCK up to 8MHz
Figure 10: SPI Timing of Read Access with pause (tPAUSE) of 500 ns with fSCK up to 8MHz.
©2020 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany
Terms of delivery and rights to technical change reserved.
Download newest version at www.trinamic.com