Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17
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Name Pin IO Description
GPIO6 / AENC_VN_MCD / DBGSPI_MISO 4 IO GPIO or ∆Σ-Demodulator clock input MCLKI, clock
output MCLKO, or single bit DAC output MDAC for
AGPI_A_MCD, SPI debug port pin DBGSPI_MISO
GPIO7 / AENC_WY_MCD / DBGSPI_TRG 5 IO GPIO or ∆Σ-Demodulator clock input MCLKI, clock
output MCLKO, or single bit DAC output MDAC for
AGPI_B_MCD, SPI debug port pin DBGSPI_TRG
PWM_IDLE_H 59 I idle level of high side gate control signals (not
used)
PWM_IDLE_L 60 I idle level of low side gate control signals (not used)
PWM_UX1_H 39 O high side gate control output U (3-phase) resp. X1
(2-phase)
PWM_UX1_L 40 O low side gate control output U (3-phase) resp. X1
(2-phase)
PWM_VX2_H 41 O high side gate control output V (3-phase) resp. X2
(2-phase)
PWM_VX2_L 42 O low side gate control output V (3-phase) resp. X2
(2-phase)
PWM_WY1_H 46 O high side gate control output W (3-phase) resp. Y1
(2-phase)
PWM_WY1_L 47 O low side gate control output W (3-phase) resp. Y1
(2-phase)
PWM_Y2_H 48 O high side gate control output Y2 (2-phase only)
PWM_Y2_L 49 O low side gate control output Y2 (2-phase only)
BRAKE 31 O brake chopper control output signal
Table 28: Functional Pin Description
Feedback input pins that are not needed in target application can be left open or tied to GND.
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