Datasheet

TMC4671 Datasheet • IC Version V1.3 | Document Revision V2.00 • 2020-Apr-17
103 / 142
7.3 Register Map - Defaults, Data Fields (Bit Masks), min, max
RD/WR ADDR NAME DEFAULT MIN MAX COMMENT
R 0x00
h
CHIPINFO_DATA
SI_TYPE 0x0
h
0x0
h
0xFFFFFFFF
h
SI_VERSION 0x0
h
0x0
h
0xFFFFFFFF
h
SI_DATE 0x0
h
0x0
h
0xFFFFFFFF
h
SI_TIME 0x0
h
0x0
h
0xFFFFFF
h
SI_VARIANT 0x0
h
0x0
h
0xFFFFFFFF
h
SI_BUILD 0x0
h
0x0
h
0xFFFFFFFF
h
RW 0x01
h
CHIPINFO_ADDR
CHIP_INFO_ADDRESS 0x0
h
0x0
h
0x5
h
R 0x02
h
ADC_RAW_DATA
ADC_I0_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_I1_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_VM_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_AGPI_A_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_AGPI_B_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_AENC_UX_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_AENC_VN_RAW 0x0
h
0x0
h
0xFFFF
h
ADC_AENC_WY_RAW 0x0
h
0x0
h
0xFFFF
h
RW 0x03
h
ADC_RAW_ADDR
ADC_RAW_ADDR 0x0
h
0x0
h
0x3
h
RW 0x04
h
dsADC_MCFG_B_
MCFG_A
cfg_dsmodulator_a 0x0
h
0x0
h
0x3
h
mclk_polarity_a 0x0
h
0x0
h
0x1
h
mdat_polarity_a 0x0
h
0x0
h
0x1
h
sel_nclk_mclk_i_a 0x0
h
0x0
h
0x1
h
blanking_a 0x0
h
0x0
h
0xFF
h
cfg_dsmodulator_b 0x0
h
0x0
h
0x3
h
mclk_polarity_b 0x0
h
0x0
h
0x1
h
mdat_polarity_b 0x0
h
0x0
h
0x1
h
sel_nclk_mclk_i_b 0x0
h
0x0
h
0x1
h
blanking_b 0x0
h
0x0
h
0xFF
h
RW 0x05
h
dsADC_MCLK_A
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