TRM-1 Low-band RF Power Amplifier Deleted: Formatted Product Requirements Document Deleted: Version 1A¶ Revised August 20, 2003 Deleted: April 147, 200331057 Deleted: May 3, 2003 Deleted: July 1, 2003nely31 Deleted: T Vytek Wireless Wireless Products Division 2310 Cousteau Court Vista, CA 92083, USA (760) 536-1000 www.vytek.
TABLE OF CONTENTS Deleted: Technical Brief 3¶ Scope 3¶ Functionality 3¶ Design Philosophy 3¶ Robustness 3¶ Implementation and Construction 3¶ Operation 4¶ Specifications 4¶ Hardware Block Diagram 6¶ Interface Definitions 7¶ Power Supply Connector 7¶ Power Amplifier Module Connector 8¶ Filter / Coupler Module Connector 8¶ Rear Panel DC Power Connector 9¶ Rear Panel RS232 Connector 9¶ Controller Connections 10¶ FPGA Register Definitions 12¶ Software Description 13¶ Alarms Types & Behavior 13¶ Power Amplifier
Deleted: ¶ John Sonnenberg¶ Vytek Wireless¶ Vista, CA ¶ ¶ Technical Brief Scope Page Break The scope of this PRD is to describe the technical implementation of a custom modular Low-Band RF Power Amplifier Unit. The PA is part of a wide-area data network base station. It is non-linear, with redundancy built-in for extra reliability and up-time. Functionality The amplifier takes in a constant-envelope (CE) RF signal at a level of approximately 5dBm, and amplifies it to a level of 56dBm (400 watts).
Operation The amplifier should look like a gain block, with some AGC for power leveling. It powers up in the “on” state. Deleted: Expected Operating Performance Specifications Parameter Customer Specification Design Goals Temperature Range Shock 0 to +50 C ambient -30 to +60 C Size 19” rack mount, 6 U tall, 17” deep.
< TBD Amps power to power amp. Battery MUST be present in order to ensure operation of controller when amplifier power is off. Control Interfaces Serial port for local console Measurements Voltages, currents, forward and reflected RF power, temperature, fan health, alarms, PA stage in use. Via Control Serial port. Alarms Console Protocol Network Protocols Connectors Firmware update Soft-fail modes Hard reset input Internal Measurement Accuracy RF leveling time constant for changes in drive level.
Deleted: Hardware Block Diagram LEDs Fans TRM-1 Power Amplifier VyTek Wireless Battery Input Tx Alarm 10 to 18 volts External I/O Connector Control Power Supply Module 48 volts 110 VAC Input 48 volts Power Supply Module Voltage Regulators and Switches 15 volts Atmel ATmega128 Processor 5 volts FPGA Atmel EP1K30 DAC Outputs A/D Inputs Control Controller Module Supply Power Input Power Analog Controls and Status Temp Sensor LPF Driver Limiting Amplifier Power Amplifier Power Amplifier M
Interface Definitions Power Supply Connector Pin 1 2 3 4 5 6 Name +Vout +Vout GND GND -Sense Vout Adjust 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OC Alarm Iout Monitor Share Bus Enable +Vout +Vout GND GND +Sense NC V Shift OV Alarm GND Rect Fail +Vout GND GND GND SD0 SD1 AC Sense OV Adjust 29 30 Lamp Test On / Off Function Output Voltage Output Voltage Output Return Output Return Connect to Ground Output Voltage Control. Vout = 59v – 2.42v – 1.8 x {Vout Adjust} 59v – 2.42v – 1.
Deleted: Table : Controller: Rear Panel I/O Connector Formatted Power Amplifier Module Connector Pin A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name GND +48V Installed Deleted: In1 Pwr Deleted: Fwd Bias I/O Input Input Output Function High Current Ground High Current Power Supply (+48 volts) “Amplifier Installed” signal to the Controller. Connected to Ground inside of the PA. Floats high when module is not plugged-in.
Rear Panel DC Power Connector Pin 1 Name Monitor 2 3 4 Gnd Gnd Battery Function Controller Power Monitor (Don’t apply an external voltage to this pin, but it may be used to monitor the actual controller voltage if desired.
Controller Connections Pin J1-1 J1-2 J1-3 Name +5v Temp 2 Gnd I/O Output Input Logical Connection Voltage Regulator CPU ADC2 Function +5 Volts from Controller Temperature Sensor Signal from Amp #2 Pin J2-1 Name Fan1 I/O Input Function Fan #1 current sensor analog signal J2-2 Fan2 Input J2-4 Fan_On Output J2-5 Alarm LED1 Output Logical Connection FANA MUX to CPU ADC6 FANB MUX to CPU ADC6 FANC MUX to CPU ADC6 FPGA Pin 130 -> Q6 FET Switch CPU PB0 J2-6 Alarm LED2 Output CPU PB6 J2-7 J2-8
J15-9 J15-10 Amp 2 Inst (intspi_clk) J15-11 Fwd Power (fwd_pwr) J15-12 Fwd Offset (fwd_offset) J15-13 PS1 AC (intspi_reset) J15-14 PS2 AC (intspi_miso) J15-15 J15-16 Pin Name J16-1 J16-2 J16-3 J16-4 J16-5 J16-6 J17-1 J17-2 TP15 FPGA Pin 67 Input CPU ADC0 0 = Amplifier 2 Installed (Must be pulled up by FPGA.) Forward Power Detector Analog Signal Output DAC U11-A Bias Voltage for Forward Power Detector Input FPGA Pin 70 Input Inverter -> FPGA Pin 68 NC NC Low = AC is < 60 VAC.
(extspi_a1) RF Detect 2 (extspi_a0) J17-8 PS1 OV (extspi_clk) J17-9 PS1 OC (extspi_mosi) J17-10 (extspi_miso) J17-7 Input Input Input Output J17-11 PS2 OV (extspi_backplid0) J17-12 PS2 OC (extspi_backplid1) J17-13 J17-14 J17-15 J17-16 Input Input FPGA Pin 37 Inverter -> FPGA Pin 36 Inverter -> FPGA Pin 46 Inverter -> FPGA Pin 48 Inverter -> FPGA Pin 47 Inverter -> FPGA Pin 83 Inverter -> FPGA Pin 86 (0 = No, 1 = Yes) RF Detected at Power Amplifier 2 (0 = No, 1 = Yes) Over Voltage Alarm Over Current Ala
0 1 0 1 7 Read (1 = OK, 0 = Alarm) PS2 Status: (0 = Failure, 1 = OK) 0 1 1 0 7-0 R/W Read / Write Scratch Register 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 Read Read Read Read Read Read Read Read Amp 1 Installed (1 = No, 0 = Yes) RF Detect 1 (0 = No, 1 = Yes) NC – Read as 0 NC – Read as 0 Amp 2 Installed (1 = No, 0 = Yes) RF Detect 2 (0 = No, 1 = Yes) NC – Read as 0 NC – Read as 0 1 1 0 0 0 0 0 0 0 1 Write Write 1 1 0 0 0 0 0 0 2 3 Write
Status information for both PA #1 and PA #2 is read via a 3 byte (24-bit) status word called PAStatusWord24, as described below. The amplifier sets the bit when the relevant condition occurs. The bit will stay set until cleared by a write of a 0 to the corresponding bit in the status register –OR– when the alarming amplifier is removed or taken offline, then manually brought back online (the failure count will also be cleared in this case).
Power Supply Alarms In addition to the power amplifier alarms, Status information for both PS #1 and PS #2 is read via a 2 byte (16bit) status word called PSStatusWord16, as described below. The amplifier sets the bit when the relevant condition occurs. The bit will stay set until cleared by a write of a 0 to the corresponding bit in the status register.
Alarm Algorithms Several alarm scenarios are described in the flow diagrams below.
State Machine TRM-1 CPU Controller: State Machine Initialization RFdetect == 0? no RampUp no true? yes yes RampUp = true RampUp = false Read forward pwr atten = (0.03125*(FwdTarg - FwdRead)) / 0.
PA Cutover PAx fail: Cutover to PAy PSx disable PAy fail counter >= MAXFAIL yes no PSy switch off? yes no CLI cmd override? yes no PSy enable Deselect PAx, select PAy Return to State Machine Manual PA/PS Offline Manual PA/PS offline mgmt PS x currently offline (switch or SW)? yes no PA x currently installed? no yes Clear PA x alarms Clear PA x fail counter Vytek TRM-1 PRD Return to State Machine 18
Serial Port Commands available to User The table below lists all of the serial commands available to the user. All configuration parameters that are modified using the serial commands are stored in non-volatile memory and will be applied through subsequent power/reset cycles. CMD PARAMETERS CUrrent Units of Measure Range Amps 0 –- 40 Resolution Default Value 0.01 MEANING/ACTION Get the DC supply current DOWNLOAD Start xmodem1k download Failcount m FWd m Watts 250 - 500 1-255 5 0.
Deleted: Alarm Behaviour¶ All Warn and Shutdown flags remain Deleted: Serial Port Commands available to User¶ CMD ... [31] LEDs Formatted: Bullets and Numbering PA #1 and PA #2 will each have LEDs indicating their status, as well as a single Tx LED indicating the presence of RF output greater than 10 Watts.
Page 2: [1] Deleted Lori Welte 7/2/2003 11:20:00 AM Technical Brief.....................................................................................................................3 Scope................................................................................................................................3 Functionality ....................................................................................................................3 Design Philosophy ......................................
FPGA Register Definitions ............................................................................................12 Software Description .........................................................................................................13 Alarms Types & Behavior .............................................................................................13 Power Amplifier Alarms............................................................................................13 Power Supply Alarms .....
Implementation and Construction...................................................................................... Operation............................................................................................................................ Specifications......................................................................................................................... System .....................................................................................................................
Software Description ...........................................................................................................9 Alarms Types & Behavior ...............................................................................................9 Power Amplifier Alarms..............................................................................................9 Power Supply Alarms ................................................................................................
Design Philosophy ...............................................................................................................3 Robustness .......................................................................................................................3 Implementation and Construction....................................................................................3 Specifications......................................................................................................................
Page 2: [11] Formatted Art Lashbrook 4/10/2003 7:19:00 PM Art Lashbrook 4/10/2003 7:19:00 PM Lori Welte 7/2/2003 11:21:00 AM Formatted Page 2: [11] Formatted Formatted Page 2: [12] Deleted Table 1: Specifications......................................................................................................................................... Table 2: Power Supply Connector .......................................................................................................................
Table 2: Power Supply Connector ....................................................................................................................... Table 5: Power Amplifier Connector................................................................................................................... Table 6: Rear Panel RS232 Connector ................................................................................................................ Table 7: Power Amplifier Alarms..............................
Formatted Page 2: [17] Formatted Art Lashbrook 4/10/2003 5:39:00 PM Art Lashbrook 4/10/2003 5:39:00 PM Art Lashbrook 4/10/2003 5:40:00 PM Art Lashbrook 4/10/2003 5:40:00 PM Art Lashbrook 4/10/2003 5:40:00 PM Art Lashbrook 4/10/2003 5:40:00 PM Art Lashbrook 4/10/2003 7:19:00 PM Art Lashbrook 4/10/2003 7:19:00 PM Art Lashbrook 4/10/2003 7:17:00 PM Formatted Page 2: [17] Formatted Formatted Page 2: [17] Formatted Formatted Page 2: [17] Formatted Formatted Page 2: [17] Formatted Formatted
Formatted Page 2: [19] Formatted Art Lashbrook 4/10/2003 7:17:00 PM Art Lashbrook 4/10/2003 7:17:00 PM Art Lashbrook 4/10/2003 7:17:00 PM Formatted Page 2: [19] Formatted Formatted Page 2: [19] Formatted Formatted Page 8: [20] Deleted Lori Welte 4/10/2003 11:18:00 AM Lori Welte 4/10/2003 11:18:00 AM Driver Bias Page 8: [20] Deleted Driver Bias Signal Page 8: [21] Deleted Art Lashbrook 4/10/2003 5:46:00 PM Art Lashbrook 4/10/2003 5:53:00 PM Page 8: [22] Deleted Art Lashbrook 5/29/2003 1
Page 8: [26] Deleted Art Lashbrook 4/10/2003 5:51:00 PM Page 8: [27] Deleted John Greene 5/2/2003 1:43:00 PM Page 8: [27] Deleted John Greene 5/2/2003 1:43:00 PM Page 8: [27] Deleted John Greene 5/2/2003 1:43:00 PM Page 8: [27] Deleted John Greene 5/2/2003 1:43:00 PM s 0 #1 1 #2 Page 8: [28] Deleted Art Lashbrook 4/10/2003 5:51:00 PM Page 8: [28] Deleted Art Lashbrook 4/10/2003 5:51:00 PM Page 8: [29] Deleted Art Lashbrook 5/29/2003 12:42:00 PM Art Lashbrook 4/10/2003 5:54:00 PM Pa
REFAlarm m Display or set the reflected power alarm 0-600 Status m Display the amplifier status and alarms (if no parameter), else Set the Status word to m 0-255 TEmp A Gets linear Amp temperature -40 to +100 TEmp P Gets PreDriver temperature -40 to +100 Gets DC supply voltage 0.0-40.0 Voltage Design Philosophy Robustness The design will incorporate, to the extent feasible and cost effective, margin against the specified criteria.
AC power supply, two per unit. Load-sharing, each with enough capacity to output 1500 watts if needed. Operation The amplifier should look like a gain block, with some AGC for power leveling. It powers up in the “on” state. Status Word Definition Status byte For all bits except bit 6, the amplifier sets the bit when the relevant condition occurs. The bit will stay set until cleared by a write of a 1 to the corresponding bit in the control register.
7 6 5 4 3 2 1 0 Fan Warn Amp Online Reset Active Overdrive Warn Thermal Warn Overdrive Shutdown Thermal Shutdown 1 fan current has exceeded or fallen below fixed high/low thresholds 0 fan current is within fixed high/low thresholds 1 amp is online 0 amp is shutdown 1 performs a hardware reset on controller 0 controller is running 1 amp #2 is currently active 0 amp #1 is currently active 1 output power exceeds fixed warn threshold 0 output power is below fixed warn threshol
