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Table Of Contents
UniStone
1 General Device Overview
1.1 Features
1.2 Block Diagram
1.3 Pin Configuration LGA
1.4 Pin Description
1.5 System Integration
1.6 FW version
2 Basic Operating Information
2.1 Power Supply
2.2 Clocking
3 Interfaces
3.1 HCI / UART Interface
3.1.1 Supported Transport Layers
3.1.2 UART
3.1.2.1 Baud Rates
3.2 PCM Interface
3.2.1 Overview
3.3 WLAN Coexistence Interface
4 General Device Capabilities
4.1 HCI+ and Bluetooth Device Data (BD_DATA)
4.2 Manufacturer Mode
4.3 Firmware ROM Patching
4.3.1 Patch Support
5 Bluetooth Capabilities
5.1 Supported Features
5.2 UniStone Specifics and Extensions
5.2.1 During Connection
5.2.1.1 Scatternet and Piconet Capabilities
5.2.1.2 Role Switch
5.2.1.3 Dynamic Polling Strategy
5.2.1.4 Adaptive Frequency Hopping (AFH)
5.2.1.5 Channel Quality Driven Data Rate Change (CQDDR)
5.2.2 Synchronous Links
5.2.2.1 Interface
5.2.2.2 Voice Coding
5.2.3 RSSI and Output Power Control
5.2.3.1 Received Signal Strength Indication (RSSI)
5.2.3.2 Output Power Control
5.2.3.3 Ultra Low Transmit Power
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
6.2 Operating Conditions
6.3 DC Characteristics
6.3.1 Pad Driver and Input Stages
6.3.2 Pull-ups and Pull-downs
6.3.3 Protection Circuits
6.4 AC Characteristics
6.4.1 Characteristics of 32.768 kHz Clock Signal
6.5 RF Part
6.5.1 Characteristics RF Part
6.5.1.1 Bluetooth Related Specifications
7 Package Information
7.1 Package marking
7.2 Production Package
7.2.1 Pin mark
8 Acronyms & Abbreviations
UniStone
General Device Capabilities
Product Overview
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T3130-8XV10PO5-7600, 2007-01-31
combination of code and data. Please cons
ult manufacturer for latest information of
available patches.
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