User's Manual

UniStone
Interfaces
Product Overview 18 T3130-8XV10PO5-7600, 2007-01-31
3.2.1 Overview
The PCM interface consists of four signals as shown in Figure 3-2 below
The clock signal PCMCLK is the timing base for the other signals in the PCM interface.
In clock master mode, UniStone generates PCMCLK from the internal system clock
using a fractional divider. In clock slave mode PCMCLK is an input to UniStone and has
to be supplied by an external source. The maximum PCMCLK frequency (in both modes)
is 1/8 of the internal system clock frequency.
The PCM interface supports up to two bidirectional channels. Data is transmitted on
PCMOUT and received on PCMIN, always with the most significant bit first. The
hardware supports a Data Word Length of 16 or 24 bits. The firmware always uses 16
bits since that is the maximum audio sample size (linear samples can be up to 16 bits,
A-law or µ-law compressed samples are always 8 bits).
The samples are organized in frames such that each frame contains one sample in each
direction of each active channel. The frame rate (i.e. sample rate) is controlled by the
PCMCLK frequency and the programmable Frame Length. In the firmware the sample
rate has been fixed to 8 kHz. This means that the PCMCLK frequency can be calculated
from Frame Length and does not have to be specified.
Channel 1 has a frame signal (PCMFR1) that indicates where in the frame the channel
starts. The Frame Signal Length is programmable.
In frame master mode, UniStone generates PCMFR1. In frame slave mode the signal
PCMFR1 is an input to UniStone and has to be supplied externally.
Figure 3-2 PCM Signals Overview
PCMCLK
PCMIN
PCMFR1
PCMOUT
M
S
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
L
S
B
M
S
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
L
S
B
M
S
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
L
S
B
M
S
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
L
S
B
M
S
B
1
4
1
3
1
2
M
S
B
1
4
1
3
1
2
IDLE IDLE
Don’t Care Don’t Care
Channel 2 Start PositionFrame Signal Length
Data Word Length
Frame Length