User's Manual

UniStone
General Device Overview
Product Overview 11 T3130-8XV10PO5-7600, 2007-01-31
1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset.
If JTAG interface is not selected the port is tristate.
Descriptions of acronyms used in the pin list:
E6 P0.5/
UARTRXD
I/O/OD VDDUART Z Z Port 0.5 or
UART receive data
F2 P1.2/
TDI/
RF_ACTIVE
I/O/OD Internal2 PU
1)
PU
1)
Port 1.2 or
JTAG interface or
WLAN coexistence interface
F3 P0.11/
TX_CONF
I/O/OD Internal2 Z Z Port 0.11or
WLAN coexistence interface
F4 P0.14/
TX_CONF
I/O VDDUART Z Z Port 0.14 or
WLAN coexistence interface
F5 P0.7/
UARTCTS
I/O/OD VDDUART Z Z Port 0.7 or
UART CTS flow control
F7 P0.4/
UARTTXD
I/O/OD VDDUART PU PU Port 0.4 or
UART transmit data
F8 P0.6/
UARTRTS
I/O/OD VDDUART PU PU Port 0.6 or
UART RTS flow control
A4, A5, A6 VSUPPLY SI - - Power supply
C1 VREG SO - - Regulated Power supply
F6 VDDUART SI - - UART interface Power supply
C5 VDDPCM SI - - PCM interface Power supply
A1, A7, A9, C8,
C9, D7, D8, E8,
E9, F1, F9
VSS - - Ground
Acronym Description
I Input
O Output
OD Output with open drain capability
Z Tristate
PU Pull-up
PD Pull-down
A Analog (e.g. AI means analog input)
S Supply (e.g. SO means supply output)
Pin No. Symbol Input/
Output
Supply
voltage
During
Reset
After
Reset
Function